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author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-01-13 00:42:35 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-01-13 00:42:35 +0300 |
commit | c736c9a9553f9cfcb1b03e65f91bc29fc6446fd3 (patch) | |
tree | 458e089b267d6ef50fece5af3e95aae392dc5c73 /drivers/clk/samsung | |
parent | 576db73424305036a6aa9e40daf7109742fbb1df (diff) | |
parent | 4f964cfef39d48a8e6748847df9a1ed310b96c4e (diff) | |
download | linux-c736c9a9553f9cfcb1b03e65f91bc29fc6446fd3.tar.xz |
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Only a couple new SoCs have support added this time, primarily for
Qualcomm SM8650 based on the diffstat. Otherwise this is a collection
of non-critical fixes and cleanups to various clk drivers and their DT
bindings.
Nothing is changed in the core clk framework this time, although
there's a patch to fix a basic clk type initialization function. In
general, this pile looks to be on the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas
RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling
separate memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000
and QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: mediatek: add drivers for MT7988 SoC
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
dt-bindings: clock: mediatek: add clock controllers of MT7988
dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
dt-bindings: clock: mediatek: add MT7988 clock IDs
clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: clk-mux: Support custom parent indices for muxes
dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
clk: starfive: Add flags argument to JH71X0__MUX macro
clk: imx: pll14xx: change naming of fvco to fout
clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()
clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw
clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
clk: qcom: dispcc-sm8550: Update disp PLL settings
clk: qcom: gpucc-sm8550: Update GPU PLL settings
...
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r-- | drivers/clk/samsung/clk-cpu.h | 30 | ||||
-rw-r--r-- | drivers/clk/samsung/clk.h | 157 |
2 files changed, 101 insertions, 86 deletions
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index fc9f67a3b22e..0164bd9ad021 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -11,10 +11,10 @@ #include "clk.h" /** - * struct exynos_cpuclk_data: config data to setup cpu clocks. - * @prate: frequency of the primary parent clock (in KHz). - * @div0: value to be programmed in the div_cpu0 register. - * @div1: value to be programmed in the div_cpu1 register. + * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks + * @prate: frequency of the primary parent clock (in KHz) + * @div0: value to be programmed in the div_cpu0 register + * @div1: value to be programmed in the div_cpu1 register * * This structure holds the divider configuration data for dividers in the CPU * clock domain. The parent frequency at which these divider values are valid is @@ -29,17 +29,17 @@ struct exynos_cpuclk_cfg_data { }; /** - * struct exynos_cpuclk: information about clock supplied to a CPU core. - * @hw: handle between CCF and CPU clock. - * @alt_parent: alternate parent clock to use when switching the speed - * of the primary parent clock. - * @ctrl_base: base address of the clock controller. - * @lock: cpu clock domain register access lock. - * @cfg: cpu clock rate configuration data. - * @num_cfgs: number of array elements in @cfg array. - * @clk_nb: clock notifier registered for changes in clock speed of the - * primary parent clock. - * @flags: configuration flags for the CPU clock. + * struct exynos_cpuclk - information about clock supplied to a CPU core + * @hw: handle between CCF and CPU clock + * @alt_parent: alternate parent clock to use when switching the speed + * of the primary parent clock + * @ctrl_base: base address of the clock controller + * @lock: cpu clock domain register access lock + * @cfg: cpu clock rate configuration data + * @num_cfgs: number of array elements in @cfg array + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock + * @flags: configuration flags for the CPU clock * * This structure holds information required for programming the CPU clock for * various clock speeds. diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index ab9c3d7a25b3..516b716407e5 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -14,11 +14,11 @@ #include "clk-pll.h" /** - * struct samsung_clk_provider: information about clock provider - * @reg_base: virtual address for the register base. - * @dev: clock provider device needed for runtime PM. - * @lock: maintains exclusion between callbacks for a given clock-provider. - * @clk_data: holds clock related data like clk_hw* and number of clocks. + * struct samsung_clk_provider - information about clock provider + * @reg_base: virtual address for the register base + * @dev: clock provider device needed for runtime PM + * @lock: maintains exclusion between callbacks for a given clock-provider + * @clk_data: holds clock related data like clk_hw* and number of clocks */ struct samsung_clk_provider { void __iomem *reg_base; @@ -29,10 +29,10 @@ struct samsung_clk_provider { }; /** - * struct samsung_clock_alias: information about mux clock - * @id: platform specific id of the clock. - * @dev_name: name of the device to which this clock belongs. - * @alias: optional clock alias name to be assigned to this clock. + * struct samsung_clock_alias - information about mux clock + * @id: platform specific id of the clock + * @dev_name: name of the device to which this clock belongs + * @alias: optional clock alias name to be assigned to this clock */ struct samsung_clock_alias { unsigned int id; @@ -50,12 +50,12 @@ struct samsung_clock_alias { #define MHZ (1000 * 1000) /** - * struct samsung_fixed_rate_clock: information about fixed-rate clock - * @id: platform specific id of the clock. - * @name: name of this fixed-rate clock. - * @parent_name: optional parent clock name. - * @flags: optional fixed-rate clock flags. - * @fixed-rate: fixed clock rate of this clock. + * struct samsung_fixed_rate_clock - information about fixed-rate clock + * @id: platform specific id of the clock + * @name: name of this fixed-rate clock + * @parent_name: optional parent clock name + * @flags: optional fixed-rate clock flags + * @fixed_rate: fixed clock rate of this clock */ struct samsung_fixed_rate_clock { unsigned int id; @@ -74,14 +74,14 @@ struct samsung_fixed_rate_clock { .fixed_rate = frate, \ } -/* - * struct samsung_fixed_factor_clock: information about fixed-factor clock - * @id: platform specific id of the clock. - * @name: name of this fixed-factor clock. - * @parent_name: parent clock name. - * @mult: fixed multiplication factor. - * @div: fixed division factor. - * @flags: optional fixed-factor clock flags. +/** + * struct samsung_fixed_factor_clock - information about fixed-factor clock + * @id: platform specific id of the clock + * @name: name of this fixed-factor clock + * @parent_name: parent clock name + * @mult: fixed multiplication factor + * @div: fixed division factor + * @flags: optional fixed-factor clock flags */ struct samsung_fixed_factor_clock { unsigned int id; @@ -103,16 +103,16 @@ struct samsung_fixed_factor_clock { } /** - * struct samsung_mux_clock: information about mux clock - * @id: platform specific id of the clock. - * @name: name of this mux clock. - * @parent_names: array of pointer to parent clock names. - * @num_parents: number of parents listed in @parent_names. - * @flags: optional flags for basic clock. - * @offset: offset of the register for configuring the mux. - * @shift: starting bit location of the mux control bit-field in @reg. - * @width: width of the mux control bit-field in @reg. - * @mux_flags: flags for mux-type clock. + * struct samsung_mux_clock - information about mux clock + * @id: platform specific id of the clock + * @name: name of this mux clock + * @parent_names: array of pointer to parent clock names + * @num_parents: number of parents listed in @parent_names + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the mux + * @shift: starting bit location of the mux control bit-field in @reg + * @width: width of the mux control bit-field in @reg + * @mux_flags: flags for mux-type clock */ struct samsung_mux_clock { unsigned int id; @@ -146,14 +146,16 @@ struct samsung_mux_clock { __MUX(_id, cname, pnames, o, s, w, f, mf) /** - * @id: platform specific id of the clock. - * struct samsung_div_clock: information about div clock - * @name: name of this div clock. - * @parent_name: name of the parent clock. - * @flags: optional flags for basic clock. - * @offset: offset of the register for configuring the div. - * @shift: starting bit location of the div control bit-field in @reg. - * @div_flags: flags for div-type clock. + * struct samsung_div_clock - information about div clock + * @id: platform specific id of the clock + * @name: name of this div clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the div + * @shift: starting bit location of the div control bit-field in @reg + * @width: width of the bitfield + * @div_flags: flags for div-type clock + * @table: array of divider/value pairs ending with a div set to 0 */ struct samsung_div_clock { unsigned int id; @@ -190,14 +192,14 @@ struct samsung_div_clock { __DIV(_id, cname, pname, o, s, w, 0, 0, t) /** - * struct samsung_gate_clock: information about gate clock - * @id: platform specific id of the clock. - * @name: name of this gate clock. - * @parent_name: name of the parent clock. - * @flags: optional flags for basic clock. - * @offset: offset of the register for configuring the gate. - * @bit_idx: bit index of the gate control bit-field in @reg. - * @gate_flags: flags for gate-type clock. + * struct samsung_gate_clock - information about gate clock + * @id: platform specific id of the clock + * @name: name of this gate clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the gate + * @bit_idx: bit index of the gate control bit-field in @reg + * @gate_flags: flags for gate-type clock */ struct samsung_gate_clock { unsigned int id; @@ -226,9 +228,9 @@ struct samsung_gate_clock { #define PNAME(x) static const char * const x[] __initconst /** - * struct samsung_clk_reg_dump: register dump of clock controller registers. - * @offset: clock register offset from the controller base address. - * @value: the value to be register at offset. + * struct samsung_clk_reg_dump - register dump of clock controller registers + * @offset: clock register offset from the controller base address + * @value: the value to be register at offset */ struct samsung_clk_reg_dump { u32 offset; @@ -236,14 +238,15 @@ struct samsung_clk_reg_dump { }; /** - * struct samsung_pll_clock: information about pll clock - * @id: platform specific id of the clock. - * @name: name of this pll clock. - * @parent_name: name of the parent clock. - * @flags: optional flags for basic clock. - * @con_offset: offset of the register for configuring the PLL. - * @lock_offset: offset of the register for locking the PLL. - * @type: Type of PLL to be registered. + * struct samsung_pll_clock - information about pll clock + * @id: platform specific id of the clock + * @name: name of this pll clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @con_offset: offset of the register for configuring the PLL + * @lock_offset: offset of the register for locking the PLL + * @type: type of PLL to be registered + * @rate_table: array of PLL settings for possible PLL rates */ struct samsung_pll_clock { unsigned int id; @@ -302,39 +305,51 @@ struct samsung_clock_reg_cache { unsigned int rsuspend_num; }; +/** + * struct samsung_cmu_info - all clocks information needed for CMU registration + * @pll_clks: list of PLL clocks + * @nr_pll_clks: count of clocks in @pll_clks + * @mux_clks: list of mux clocks + * @nr_mux_clks: count of clocks in @mux_clks + * @div_clks: list of div clocks + * @nr_div_clks: count of clocks in @div_clks + * @gate_clks: list of gate clocks + * @nr_gate_clks: count of clocks in @gate_clks + * @fixed_clks: list of fixed clocks + * @nr_fixed_clks: count clocks in @fixed_clks + * @fixed_factor_clks: list of fixed factor clocks + * @nr_fixed_factor_clks: count of clocks in @fixed_factor_clks + * @nr_clk_ids: total number of clocks with IDs assigned + * @cpu_clks: list of CPU clocks + * @nr_cpu_clks: count of clocks in @cpu_clks + * @clk_regs: list of clock registers + * @nr_clk_regs: count of clock registers in @clk_regs + * @suspend_regs: list of clock registers to set before suspend + * @nr_suspend_regs: count of clock registers in @suspend_regs + * @clk_name: name of the parent clock needed for CMU register access + */ struct samsung_cmu_info { - /* list of pll clocks and respective count */ const struct samsung_pll_clock *pll_clks; unsigned int nr_pll_clks; - /* list of mux clocks and respective count */ const struct samsung_mux_clock *mux_clks; unsigned int nr_mux_clks; - /* list of div clocks and respective count */ const struct samsung_div_clock *div_clks; unsigned int nr_div_clks; - /* list of gate clocks and respective count */ const struct samsung_gate_clock *gate_clks; unsigned int nr_gate_clks; - /* list of fixed clocks and respective count */ const struct samsung_fixed_rate_clock *fixed_clks; unsigned int nr_fixed_clks; - /* list of fixed factor clocks and respective count */ const struct samsung_fixed_factor_clock *fixed_factor_clks; unsigned int nr_fixed_factor_clks; - /* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; - /* list of cpu clocks and respective count */ const struct samsung_cpu_clock *cpu_clks; unsigned int nr_cpu_clks; - /* list and number of clocks registers */ const unsigned long *clk_regs; unsigned int nr_clk_regs; - /* list and number of clocks registers to set before suspend */ const struct samsung_clk_reg_dump *suspend_regs; unsigned int nr_suspend_regs; - /* name of the parent clock needed for CMU register access */ const char *clk_name; }; |