diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-03-03 00:41:50 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-03-31 05:26:26 +0300 |
| commit | 8c489216c3e103a24856fd676fc5f51619c2e052 (patch) | |
| tree | d18847f00d12685742da45529ff5325c269d6172 /drivers/clk/socfpga/clk-pll-a10.c | |
| parent | 2c2b9c6067170de2a63e7e3d9f5bb205b870de7c (diff) | |
| download | linux-8c489216c3e103a24856fd676fc5f51619c2e052.tar.xz | |
clk: socfpga: arria10: convert to use clk_hw
As recommended by Stephen Boyd, convert the Arria10 clock driver to use
the clk_hw registration method.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-pll-a10.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-pll-a10.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 3338f054fe98..bee0f7da5b6e 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -63,11 +63,11 @@ static const struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static struct clk * __init __socfpga_pll_init(struct device_node *node, +static struct clk_hw * __init __socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFGPA_MAX_PARENTS]; @@ -101,14 +101,14 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; + hw_clk = &pll_clk->hw.hw; - clk = clk_register(NULL, &pll_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + if (clk_hw_register(NULL, hw_clk)) { kfree(pll_clk); return NULL; } - of_clk_add_provider(node, of_clk_src_simple_get, clk); - return clk; + of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); + return hw_clk; } void __init socfpga_a10_pll_init(struct device_node *node) |