diff options
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-03-23 19:38:26 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-04-22 01:29:23 +0300 |
| commit | fa4d0ca104bfdcda7b7e2bac855b358f302fd310 (patch) | |
| tree | 14c68c6b45413a4281a7d53af3b84564400a4bf1 /drivers/clk/sunxi/Makefile | |
| parent | 7f2ea3847d47d49929d41573a3b26c80ddebbef5 (diff) | |
| download | linux-fa4d0ca104bfdcda7b7e2bac855b358f302fd310.tar.xz | |
clk: sunxi: Add PLL3 clock
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi/Makefile')
| -rw-r--r-- | drivers/clk/sunxi/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 3fd7901d48e4..e2f72797bd9a 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -11,6 +11,7 @@ obj-y += clk-a10-ve.o obj-y += clk-a20-gmac.o obj-y += clk-mod0.o obj-y += clk-simple-gates.o +obj-y += clk-sun4i-pll3.o obj-y += clk-sun8i-bus-gates.o obj-y += clk-sun8i-mbus.o obj-y += clk-sun9i-core.o |