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authorAndrew Bresticker <abrestic@chromium.org>2014-05-15 04:32:59 +0400
committerMike Turquette <mturquette@linaro.org>2014-05-23 09:14:52 +0400
commit5c992afcf8e4f91fac05d39b86c7f7922a50145c (patch)
tree349870dc6143624ca62f5cfa2aa9de3460095d20 /drivers/clk/tegra/clk-id.h
parent9d61707b1f83324fc30918787cb6ef101997ecbd (diff)
downloadlinux-5c992afcf8e4f91fac05d39b86c7f7922a50145c.tar.xz
clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
-rw-r--r--drivers/clk/tegra/clk-id.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index c39613c519af..0011d547a9f7 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -233,6 +233,7 @@ enum clk_id {
tegra_clk_xusb_hs_src,
tegra_clk_xusb_ss,
tegra_clk_xusb_ss_src,
+ tegra_clk_xusb_ss_div2,
tegra_clk_max,
};