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| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 16:10:43 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 13:41:49 +0300 |
| commit | eede7113aabd3f40f8d9c32b1690f2859fcb101a (patch) | |
| tree | ffa6885caeb0e7e1a1e1a64161a4082771cceedc /drivers/clk/tegra/clk-id.h | |
| parent | 98c4b3661b5aee0e583d17d6304f6489c0f41155 (diff) | |
| download | linux-eede7113aabd3f40f8d9c32b1690f2859fcb101a.tar.xz | |
clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
0 files changed, 0 insertions, 0 deletions