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authorLee Jones <lee.jones@linaro.org>2013-09-17 13:26:24 +0400
committerLinus Walleij <linus.walleij@linaro.org>2013-09-26 13:05:31 +0400
commitdec759d8ef01b3edd5ceb9832ce2338c6c396d11 (patch)
treecefd3860f14bf4917d9ccc96444b09a4047eccba /drivers/clk/ux500
parent82b0f4b7c576d22c764239662cedc63c21f02d8d (diff)
downloadlinux-dec759d8ef01b3edd5ceb9832ce2338c6c396d11.tar.xz
clk: ux500: Provide u8500_clk with skeleton Device Tree support
The functional components will be added on a per-clock basis. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk/ux500')
-rw-r--r--drivers/clk/ux500/u8500_of_clk.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
index ceebce6a624f..bfbe3cae72d7 100644
--- a/drivers/clk/ux500/u8500_of_clk.c
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -7,6 +7,7 @@
* License terms: GNU General Public License (GPL) version 2
*/
+#include <linux/of.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
@@ -14,13 +15,27 @@
#include <linux/platform_data/clk-ux500.h>
#include "clk.h"
+static const struct of_device_id u8500_clk_of_match[] = {
+ { .compatible = "stericsson,u8500-clks", },
+ { },
+};
+
void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
u32 clkrst5_base, u32 clkrst6_base)
{
struct prcmu_fw_version *fw_version;
+ struct device_node *np = NULL;
+ struct device_node *child = NULL;
const char *sgaclk_parent = NULL;
struct clk *clk;
+ if (of_have_populated_dt())
+ np = of_find_matching_node(NULL, u8500_clk_of_match);
+ if (!np) {
+ pr_err("Either DT or U8500 Clock node not found\n");
+ return;
+ }
+
/* Clock sources */
clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
CLK_IS_ROOT|CLK_IGNORE_UNUSED);
@@ -378,4 +393,8 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
/* Periph6 */
clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
+
+ for_each_child_of_node(np, child) {
+ /* Place holder for supported nodes. */
+ }
}