diff options
| author | Rahul Tanwar <rtanwar@maxlinear.com> | 2022-10-13 09:48:31 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-10-18 00:17:37 +0300 |
| commit | eaabee88a88a26b108be8d120fc072dfaf462cef (patch) | |
| tree | 4a3a3e92141319872856b6705e08d2e20c2d8872 /drivers/clk/x86/clk-cgu.h | |
| parent | 036177310bac5534de44ff6a7b60a4d2c0b6567c (diff) | |
| download | linux-eaabee88a88a26b108be8d120fc072dfaf462cef.tar.xz | |
clk: mxl: Remove redundant spinlocks
Patch 1/4 of this patch series switches from direct readl/writel
based register access to regmap based register access. Instead
of using direct readl/writel, regmap API's are used to read, write
& read-modify-write clk registers. Regmap API's already use their
own spinlocks to serialize the register accesses across multiple
cores in which case additional driver spinlocks becomes redundant.
Hence, remove redundant spinlocks from driver in this patch 2/4.
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a8a02c8773b88924503a9fdaacd37dd2e6488bf3.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/x86/clk-cgu.h')
| -rw-r--r-- | drivers/clk/x86/clk-cgu.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index dbcb66468797..0aa0f35d63a0 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -18,7 +18,6 @@ struct lgm_clk_mux { u8 shift; u8 width; unsigned long flags; - spinlock_t lock; }; struct lgm_clk_divider { @@ -31,7 +30,6 @@ struct lgm_clk_divider { u8 width_gate; unsigned long flags; const struct clk_div_table *table; - spinlock_t lock; }; struct lgm_clk_ddiv { @@ -49,7 +47,6 @@ struct lgm_clk_ddiv { unsigned int mult; unsigned int div; unsigned long flags; - spinlock_t lock; }; struct lgm_clk_gate { @@ -58,7 +55,6 @@ struct lgm_clk_gate { unsigned int reg; u8 shift; unsigned long flags; - spinlock_t lock; }; enum lgm_clk_type { @@ -82,7 +78,6 @@ struct lgm_clk_provider { struct device_node *np; struct device *dev; struct clk_hw_onecell_data clk_data; - spinlock_t lock; }; enum pll_type { @@ -97,7 +92,6 @@ struct lgm_clk_pll { unsigned int reg; unsigned long flags; enum pll_type type; - spinlock_t lock; }; /** |