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authorJun Nie <jun.nie@linaro.org>2016-09-06 09:02:41 +0300
committerStephen Boyd <sboyd@codeaurora.org>2016-09-14 23:48:32 +0300
commit8d9a0860b75525e3cf240bc152bfdeaeb2e562a1 (patch)
tree7e3ee13a267085c5ba5869e3ed5af020de2481aa /drivers/clk/zte/clk.h
parent6e2e7c9fdae316bfb2724d2dbf230678d3f09092 (diff)
downloadlinux-8d9a0860b75525e3cf240bc152bfdeaeb2e562a1.tar.xz
clk: zx: reform pll config info to ease code extension
Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/zte/clk.h')
-rw-r--r--drivers/clk/zte/clk.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
index 65ae08b818d3..8f6b5f05bb7f 100644
--- a/drivers/clk/zte/clk.h
+++ b/drivers/clk/zte/clk.h
@@ -24,6 +24,8 @@ struct clk_zx_pll {
const struct zx_pll_config *lookup_table; /* order by rate asc */
int count;
spinlock_t *lock;
+ u8 pd_bit; /* power down bit */
+ u8 lock_bit; /* pll lock flag bit */
};
struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
@@ -38,4 +40,6 @@ struct clk_zx_audio {
struct clk *clk_register_zx_audio(const char *name,
const char * const parent_name,
unsigned long flags, void __iomem *reg_base);
+
+extern const struct clk_ops zx_pll_ops;
#endif