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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-24 03:31:31 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-24 03:31:31 +0400
commitf01b9b73f57f4f92d39bba0d9aa4a38f318212df (patch)
treeb815a4477af34f7f6c61dff0c04db6cb975cdd55 /drivers/clk
parentfde75430278130505cac21997cd9f90b7bb2670a (diff)
parent66314223aa5e862c9d1d068cb7186b4fd58ebeaa (diff)
downloadlinux-f01b9b73f57f4f92d39bba0d9aa4a38f318212df.tar.xz
Merge tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull support for three new arm SoC types from Arnd Bergmann: - The mvebu platform includes Marvell's Armada XP and Armada 370 chips, made by the mvebu business unit inside of Marvell. Since the same group also made the older but similar platforms we call "orion5x", "kirkwood", "mv78xx0" and "dove", we plan to move all of them into the mach-mvebu directory in the future. - socfpga is Altera's platform based on Cortex-A9 cores and a lot of FPGA space. This is similar to the Xilinx zynq platform we already support. The code is particularly clean, which is helped by the fact that the hardware doesn't do much besides the parts that are expected to get added in the FPGA. - The OMAP subarchitecture gains support for the latest generation, the OMAP5 based on the new Cortex-A15 core. Support is rather rudimentary for now, but will be extended in the future. * tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits) ARM: socfpga: initial support for Altera's SOCFPGA platform arm: mvebu: generate DTBs for supported SoCs ARM: mvebu: MPIC: read number of interrupts from control register arm: mach-mvebu: add entry to MAINTAINERS arm: mach-mvebu: add compilation/configuration change arm: mach-mvebu: add defconfig arm: mach-mvebu: add documentation for new device tree bindings arm: mach-mvebu: add support for Armada 370 and Armada XP with DT arm: mach-mvebu: add source files arm: mach-mvebu: add header clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver ARM: Kconfig update to support additional GPIOs in OMAP5 ARM: OMAP5: Add the build support arm/dts: OMAP5: Add omap5 dts files ARM: OMAP5: board-generic: Add device tree support ARM: omap2+: board-generic: clean up the irq data from board file ARM: OMAP5: Add SMP support ARM: OMAP5: Add the WakeupGen IP updates ARM: OMAP5: l3: Add l3 error handler support for omap5 ARM: OMAP5: gpmc: Update gpmc_init() ... Conflicts: Documentation/devicetree/bindings/arm/omap/omap.txt arch/arm/mach-omap2/Makefile drivers/clocksource/Kconfig drivers/clocksource/Makefile
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/socfpga/Makefile1
-rw-r--r--drivers/clk/socfpga/clk.c51
3 files changed, 53 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 26b6b92942e1..3669761d1bac 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
# SoCs specific
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_MXS) += mxs/
+obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
new file mode 100644
index 000000000000..0303c0b99cd0
--- /dev/null
+++ b/drivers/clk/socfpga/Makefile
@@ -0,0 +1 @@
+obj-y += clk.o
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
new file mode 100644
index 000000000000..2c855a6394ff
--- /dev/null
+++ b/drivers/clk/socfpga/clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#define SOCFPGA_OSC1_CLK 10000000
+#define SOCFPGA_MPU_CLK 800000000
+#define SOCFPGA_MAIN_QSPI_CLK 432000000
+#define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000
+#define SOCFPGA_S2F_USR_CLK 125000000
+
+void __init socfpga_init_clocks(void)
+{
+ struct clk *clk;
+
+ clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
+ clk_register_clkdev(clk, "osc1_clk", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
+ clk_register_clkdev(clk, "mpu_clk", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
+ clk_register_clkdev(clk, "main_clk", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
+ clk_register_clkdev(clk, "dbg_base_clk", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
+ clk_register_clkdev(clk, "main_qspi_clk", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
+ clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
+ clk_register_clkdev(clk, "s2f_usr_clk", NULL);
+}