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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-07-16 18:45:37 +0400
committerDaniel Lezcano <daniel.lezcano@linaro.org>2013-07-18 17:27:15 +0400
commit137c6b3c7c63944a9cb51de0870b72f62d240f62 (patch)
tree35f7bc2835c2be7cb5e6dd0aa190b1537b527146 /drivers/clocksource/sun4i_timer.c
parent9eded23215e99338155c18f6d860859106568bb0 (diff)
downloadlinux-137c6b3c7c63944a9cb51de0870b72f62d240f62.tar.xz
clocksource: sun4i: Add clocksource and sched clock drivers
Use the second timer found on the Allwinner SoCs as a clock source and sched clock, that were both not used yet on these platforms. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers/clocksource/sun4i_timer.c')
-rw-r--r--drivers/clocksource/sun4i_timer.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index f5e227b06ad5..b581c93f20b3 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -19,6 +19,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
+#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -96,6 +97,11 @@ static struct irqaction sun4i_timer_irq = {
.dev_id = &sun4i_clockevent,
};
+static u32 sun4i_timer_sched_read(void)
+{
+ return ~readl(timer_base + TIMER_CNTVAL_REG(1));
+}
+
static void __init sun4i_timer_init(struct device_node *node)
{
unsigned long rate = 0;
@@ -117,6 +123,15 @@ static void __init sun4i_timer_init(struct device_node *node)
rate = clk_get_rate(clk);
+ writel(~0, timer_base + TIMER_INTVAL_REG(1));
+ writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
+ TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
+ timer_base + TIMER_CTL_REG(1));
+
+ setup_sched_clock(sun4i_timer_sched_read, 32, rate);
+ clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
+ rate, 300, 32, clocksource_mmio_readl_down);
+
writel(rate / (TIMER_SCAL * HZ),
timer_base + TIMER_INTVAL_REG(0));