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authorAni Sinha <ani@anisinha.ca>2021-07-16 16:32:45 +0300
committerWei Liu <wei.liu@kernel.org>2021-07-16 17:51:54 +0300
commit5f92b45c3b67e3d222caf10e2eb898af31756b67 (patch)
tree08866e267c0194be2644bc6c63d12a3721cb7eb3 /drivers/clocksource
parent6dc77fa5ac2cf26f846a51492dbe42526e26d0f2 (diff)
downloadlinux-5f92b45c3b67e3d222caf10e2eb898af31756b67.tar.xz
x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0
Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC") added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0 of this synthetic MSR will allow hyper-v guests to report invariant TSC CPU feature through CPUID. This comment adds this explanation to the code and mentions where the Intel's generic platform init code reads this feature bit from CPUID. The comment will help developers understand how the two parts of the initialization (hyperV specific and non-hyperV specific generic hw init) are related. Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Link: https://lore.kernel.org/r/20210716133245.3272672-1-ani@anisinha.ca Signed-off-by: Wei Liu <wei.liu@kernel.org>
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