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authorVictoria Milhoan <vicki.milhoan@freescale.com>2015-08-05 21:28:38 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2015-08-10 18:18:57 +0300
commit1f06ec1d48f31a454e4292f3761a4f4178bb916c (patch)
tree8dc69a307127575d7f8383cba081aeb06051b544 /drivers/crypto/caam/desc.h
parent24821c4652dbf85a69e732574874dc191a813da4 (diff)
downloadlinux-1f06ec1d48f31a454e4292f3761a4f4178bb916c.tar.xz
crypto: caam - Modify Freescale CAAM driver Scatter Gather entry definition
Modify the Scatter-Gather entry definitions for the Freescale CAAM driver to include support for both 64- and 32-bit DMA pointers. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> Tested-by: Horia Geantă <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/caam/desc.h')
-rw-r--r--drivers/crypto/caam/desc.h25
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index d397ff9d56fd..405acbf13dac 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -8,12 +8,29 @@
#ifndef DESC_H
#define DESC_H
+/*
+ * 16-byte hardware scatter/gather table
+ * An 8-byte table exists in the hardware spec, but has never been
+ * implemented to date. The 8/16 option is selected at RTL-compile-time.
+ * and this selection is visible in the Compile Time Parameters Register
+ */
+
+#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
+#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
+#define SEC4_SG_BPID_MASK 0x000000ff
+#define SEC4_SG_BPID_SHIFT 16
+#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
+#define SEC4_SG_OFFS_MASK 0x00001fff
+
struct sec4_sg_entry {
- u64 ptr;
-#define SEC4_SG_LEN_FIN 0x40000000
-#define SEC4_SG_LEN_EXT 0x80000000
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+ dma_addr_t ptr;
+#else
+ u32 rsvd1;
+ dma_addr_t ptr;
+#endif
u32 len;
- u8 reserved;
+ u8 rsvd2;
u8 buf_pool_id;
u16 offset;
};