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authorHoria Geant? <horia.geanta@freescale.com>2015-08-17 15:24:10 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2015-08-18 05:30:39 +0300
commit6c3af955935223217f23ef0ae672d3842418ec50 (patch)
treebf550c160321c337b04d1504a31738181a476a8d /drivers/crypto/caam/desc.h
parentc1ae632ad2608d0214291a64ca719f900ffef14b (diff)
downloadlinux-6c3af955935223217f23ef0ae672d3842418ec50.tar.xz
crypto: caam - add support for LS1021A
LS1021A is a QorIQ SoC having little endian CAAM. There are a few differences b/w QorIQ and i.MX from CAAM perspective: 1. i.MX platforms are somewhat special wrt. 64-bit registers: -big endian format at 64-bit level: MSW at address+0 and LSW at address+4 -little endian format at 32-bit level (within MSW and LSW) and thus need special handling. 2. No CCM (clock controller module) for QorIQ. No CAAM clocks to enable / disable. A new Kconfig option - CRYPTO_DEV_FSL_CAAM_LE - is added to indicate CAAM is little endian (*). It is hidden from the user (to avoid misconfiguration); when adding support for a new platform with LE CAAM, either the Kconfig needs to be updated or the corresponding defconfig needs to indicate that CAAM is LE. (*) Using a DT property to provide CAAM endianness would not allow for the ifdeffery. In order to keep changes to a minimum, the following changes are postponed: -endianness fix of the last word in the S/G (rsvd2, bpid, offset), fields are always 0 anyway; -S/G format fix for i.MX7 (yes, i.MX7 support was not added yet, but still...) Signed-off-by: Horia Geant? <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/caam/desc.h')
-rw-r--r--drivers/crypto/caam/desc.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index 405acbf13dac..983d663ef671 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -23,12 +23,12 @@
#define SEC4_SG_OFFS_MASK 0x00001fff
struct sec4_sg_entry {
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
- dma_addr_t ptr;
-#else
+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
u32 rsvd1;
dma_addr_t ptr;
-#endif
+#else
+ u64 ptr;
+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_IMX */
u32 len;
u8 rsvd2;
u8 buf_pool_id;