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| author | Dan Williams <dan.j.williams@intel.com> | 2022-06-06 23:32:01 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-25 22:18:07 +0300 |
| commit | 6aa41144e7f1a624062f1e66a4744c168ade1f31 (patch) | |
| tree | dbc9e873fca39bb4db419da9edc33573b28339a9 /drivers/cxl/cxl.h | |
| parent | b9686e8c8e39d4072081ef078c04915ee51c8af4 (diff) | |
| download | linux-6aa41144e7f1a624062f1e66a4744c168ade1f31.tar.xz | |
cxl/acpi: Add a host-bridge index lookup mechanism
The ACPI CXL Fixed Memory Window Structure (CFMWS) defines multiple
methods to determine which host bridge provides access to a given
endpoint relative to that device's position in the interleave. The
"Interleave Arithmetic" defines either a "standard modulo" /
round-random algorithm, or "xormap" based algorithm which can be defined
as a non-linear transform. Given that there are already more options
beyond "standard modulo" and that "xormap" may turn out to be ACPI CXL
specific, provide a callback for the region provisioning code to map
endpoint positions back to expected host bridge id (cxl_dport target).
For now just support the simple modulo math case and save the xormap for
a follow-on change.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-14-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 5e84aa2d09e2..8f39cfb0d972 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -322,11 +322,13 @@ struct cxl_switch_decoder { * struct cxl_root_decoder - Static platform CXL address decoder * @res: host / parent resource for region allocations * @region_id: region id for next region provisioning event + * @calc_hb: which host bridge covers the n'th position by granularity * @cxlsd: base cxl switch decoder */ struct cxl_root_decoder { struct resource *res; atomic_t region_id; + struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos); struct cxl_switch_decoder cxlsd; }; |