diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 02:35:06 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 18:50:41 +0300 |
| commit | 92804edb11f065aadb3a4f398bed8a846a035cd3 (patch) | |
| tree | 2adf8567035fe119669551d5951c9a5e95f3c239 /drivers/cxl | |
| parent | a12562bb70776093b270f79a4b6ef18f4bcead2b (diff) | |
| download | linux-92804edb11f065aadb3a4f398bed8a846a035cd3.tar.xz | |
cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Now that nothing external to cxl_hdm_decode_init() considers
'struct cxl_endpoint_dvec_info' move it internal to
cxl_hdm_decode_init().
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291690612.1426646.7866084245521113414.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/core/pci.c | 15 | ||||
| -rw-r--r-- | drivers/cxl/cxlpci.h | 4 | ||||
| -rw-r--r-- | drivers/cxl/mem.c | 3 |
3 files changed, 9 insertions, 13 deletions
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 0fbda1a1ca1b..7d2238edc379 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -234,14 +234,13 @@ out: /** * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint * @cxlds: Device state - * @info: DVSEC Range cached enumeration * * Try to enable the endpoint's HDM Decoder Capability */ -int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, - struct cxl_endpoint_dvsec_info *info) +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds) { struct pci_dev *pdev = to_pci_dev(cxlds->dev); + struct cxl_endpoint_dvsec_info info = { 0 }; int hdm_count, rc, i, ranges = 0; struct device *dev = &pdev->dev; int d = cxlds->cxl_dvsec; @@ -281,8 +280,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, return rc; } - info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); - if (!info->mem_enabled) + info.mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); + if (!info.mem_enabled) return 0; for (i = 0; i < hdm_count; i++) { @@ -317,7 +316,7 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK; - info->dvsec_range[i] = (struct range) { + info.dvsec_range[i] = (struct range) { .start = base, .end = base + size - 1 }; @@ -326,13 +325,13 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, ranges++; } - info->ranges = ranges; + info.ranges = ranges; /* * If DVSEC ranges are being used instead of HDM decoder registers there * is no use in trying to manage those. */ - if (!__cxl_hdm_decode_init(cxlds, info)) { + if (!__cxl_hdm_decode_init(cxlds, &info)) { dev_err(dev, "Legacy range registers configuration prevents HDM operation.\n"); return -EBUSY; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 202fdaa8d293..53cd34f8813c 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -73,7 +73,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev, int devm_cxl_port_enumerate_dports(struct cxl_port *port); struct cxl_dev_state; -struct cxl_endpoint_dvsec_info; -int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, - struct cxl_endpoint_dvsec_info *info); +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 2a5dc92d566f..8ce89d128e36 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -54,7 +54,6 @@ static void enable_suspend(void *data) static int cxl_mem_probe(struct device *dev) { struct cxl_memdev *cxlmd = to_cxl_memdev(dev); - struct cxl_endpoint_dvsec_info info = { 0 }; struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *parent_port; int rc; @@ -95,7 +94,7 @@ unlock: if (rc) return rc; - rc = cxl_hdm_decode_init(cxlds, &info); + rc = cxl_hdm_decode_init(cxlds); if (rc) return rc; |