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authorJon Hunter <jonathanh@nvidia.com>2019-05-16 18:53:54 +0300
committerVinod Koul <vkoul@kernel.org>2019-05-21 11:56:00 +0300
commit492252493ea382d12cb61c52295fc2d088bba28f (patch)
tree664e8549412de3ea80873bff8a38abb4e570d321 /drivers/dma/tegra210-adma.c
parent9ab59bf5dd6380a56e2897c92c5cd920ae4b0f8b (diff)
downloadlinux-492252493ea382d12cb61c52295fc2d088bba28f.tar.xz
dmaengine: tegra210-adma: Fix spelling
Correct spelling of 'register' in Tegra210 ADMA driver. Fixes: ded1f3db4cd6 ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/tegra210-adma.c')
-rw-r--r--drivers/dma/tegra210-adma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index 3f50fd11c380..17ea4dd99c62 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -95,7 +95,7 @@ struct tegra_adma;
* @global_int_clear: Register offset of DMA global interrupt clear.
* @ch_req_tx_shift: Register offset for AHUB transmit channel select.
* @ch_req_rx_shift: Register offset for AHUB receive channel select.
- * @ch_base_offset: Reister offset of DMA channel registers.
+ * @ch_base_offset: Register offset of DMA channel registers.
* @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
* @ch_req_mask: Mask for Tx or Rx channel select.
* @ch_req_max: Maximum number of Tx or Rx channels available.