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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2024-05-13 21:13:48 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2024-05-13 21:13:48 +0300
commit14449382b5aca53e6a31a04b1e93e53b288a1cb2 (patch)
treea3c699d1c7a838e9e5cea107c6e81b1cacdd8f69 /drivers/firmware
parenteefb5dbddd4b4c2f069cdc6f7df7e5656aede8ce (diff)
parentbf202e654bfa57fb8cf9d93d4c6855890b70b9c4 (diff)
downloadlinux-14449382b5aca53e6a31a04b1e93e53b288a1cb2.tar.xz
Merge branch 'pm-cpufreq'
Merge cpufreq updates for 6.10: - Rework the handling of disabled turbo in the intel_pstate driver and make it update the maximum CPU frequency consistently regardless of the reason on top of a number of cleanups (Rafael Wysocki). - Add missing checks for NULL .exit() cpufreq driver callback to the cpufreq core (Viresh Kumar). - Prevent pulicy->max from going above the frequency QoS maximum value when cpufreq_frequency_table_verify() is used (Xuewen Yan). - Prevent a negative CPU number or frequency value from being printed if they are really large (Joshua Yeong). - Update MAINTAINERS entry for amd-pstate to add two new submaintainers and a designated reviewer (Huang Rui). - Clean up the amd-pstate driver and update its documentation (Gautham Shenoy). - Fix the highest frequency issue in the amd-pstate driver which limits performance (Perry Yuan). - Enable CPPC v2 for certain processors in the family 17H, as requested by TR40 processor users who expect improved performance and lower system temperature (Perry Yuan). - Change latency and delay values to be read from platform firmware firstly for more accurate timing (Perry Yuan). - A new quirk is introduced for supporting amd-pstate on legacy processors which either lack CPPC capability, or only only have CPPC v2 capability (Perry Yuan). - Sun50i: Add support for opp_supported_hw, H616 platform and general cleanups (Andre Przywara, Martin Botka, Brandon Cheo Fusi, Dan Carpenter, Viresh Kumar). - CPPC: Fix possible null pointer dereference (Aleksandr Mishin). - Eliminate uses of of_node_put() (Javier Carrasco, and Shivani Gupta). - brcmstb-avs: ISO C90 forbids mixed declarations (Portia Stephens). - mediatek: Add support for MT7988A (Sam Shih). - cpufreq-qcom-hw: Add SM4450 compatibles in DT bindings (Tengfei Fan). - Fix struct cpudata::epp_cached kernel-doc in the intel_pstate cpufreq driver (Jeff Johnson). * pm-cpufreq: (46 commits) cpufreq: amd-pstate: fix the highest frequency issue which limits performance cpufreq: intel_pstate: fix struct cpudata::epp_cached kernel-doc cpufreq: Fix up printing large CPU numbers and frequency values MAINTAINERS: cpufreq: amd-pstate: Add co-maintainers and reviewer cpufreq: amd-pstate: remove unused variable lowest_nonlinear_freq cpufreq: amd-pstate: fix code format problems cpufreq: amd-pstate: Add quirk for the pstate CPPC capabilities missing cppc_acpi: print error message if CPPC is unsupported cpufreq: amd-pstate: get transition delay and latency value from ACPI tables cpufreq: amd-pstate: Bail out if min/max/nominal_freq is 0 cpufreq: amd-pstate: Remove amd_get_{min,max,nominal,lowest_nonlinear}_freq() cpufreq: amd-pstate: Unify computation of {max,min,nominal,lowest_nonlinear}_freq cpufreq: amd-pstate: Document the units for freq variables in amd_cpudata cpufreq: amd-pstate: Document *_limit_* fields in struct amd_cpudata dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles cpufreq: sun50i: fix error returns in dt_has_supported_hw() cpufreq: brcmstb-avs-cpufreq: ISO C90 forbids mixed declarations cpufreq: dt-platdev: eliminate uses of of_node_put() cpufreq: dt: eliminate uses of of_node_put() cpufreq: ti: Implement scope-based cleanup in ti_cpufreq_match_node() ...
Diffstat (limited to 'drivers/firmware')
-rw-r--r--drivers/firmware/smccc/smccc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
index db818f9dcb8e..d670635914ec 100644
--- a/drivers/firmware/smccc/smccc.c
+++ b/drivers/firmware/smccc/smccc.c
@@ -69,6 +69,7 @@ s32 arm_smccc_get_soc_id_revision(void)
{
return smccc_soc_id_revision;
}
+EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_revision);
static int __init smccc_devices_init(void)
{