diff options
| author | Tom Rix <trix@redhat.com> | 2021-05-19 19:30:56 +0300 |
|---|---|---|
| committer | Moritz Fischer <mdf@kernel.org> | 2021-07-22 05:54:21 +0300 |
| commit | 580e3137318edb39d2c6efa5dad51e3fbd7e2536 (patch) | |
| tree | 6c477a2dba5ba8d9c5500c5b923b36933bffc9b7 /drivers/fpga/zynq-fpga.c | |
| parent | 758f74674bcb82e1ed1a0b5a56980f295183b546 (diff) | |
| download | linux-580e3137318edb39d2c6efa5dad51e3fbd7e2536.tar.xz | |
fpga: fix spelling mistakes
Run the fpga subsystem through aspell.
Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Fernando Pacheco <fpacheco@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Diffstat (limited to 'drivers/fpga/zynq-fpga.c')
| -rw-r--r-- | drivers/fpga/zynq-fpga.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 07fa8d9ec675..9b75bd4f93d8 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -192,7 +192,7 @@ static void zynq_step_dma(struct zynq_fpga_priv *priv) /* Once the first transfer is queued we can turn on the ISR, future * calls to zynq_step_dma will happen from the ISR context. The - * dma_lock spinlock guarentees this handover is done coherently, the + * dma_lock spinlock guarantees this handover is done coherently, the * ISR enable is put at the end to avoid another CPU spinning in the * ISR on this lock. */ @@ -267,7 +267,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, ctrl = zynq_fpga_read(priv, CTRL_OFFSET); if (!(ctrl & CTRL_SEC_EN_MASK)) { dev_err(&mgr->dev, - "System not secure, can't use crypted bitstreams\n"); + "System not secure, can't use encrypted bitstreams\n"); err = -EINVAL; goto out_err; } @@ -344,7 +344,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, /* set configuration register with following options: * - enable PCAP interface - * - set throughput for maximum speed (if bistream not crypted) + * - set throughput for maximum speed (if bistream not encrypted) * - set CPU in user mode */ ctrl = zynq_fpga_read(priv, CTRL_OFFSET); |