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author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-08-31 02:37:00 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-08-31 02:37:00 +0300 |
commit | c66403f62717e1af3be2a1873d52d2cf4724feba (patch) | |
tree | d2cde77d83f6c1d5500b3aae2fb67fe963a287a2 /drivers/genpd/renesas/r8a774e1-sysc.c | |
parent | 4fb0dacb78c6a041bbd38ddd998df806af5c2c69 (diff) | |
parent | 5e536362f6ab97f709c07bfda962a7bb036c2563 (diff) | |
download | linux-c66403f62717e1af3be2a1873d52d2cf4724feba.tar.xz |
Merge tag 'genpd-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull ARM SoC generic power domain driver updates from Ulf Hansson:
"This adds a new subsystem for generic power domain providers in
drivers/genpd and starts moving some of the corresponding code in
there.
We have currently ~60 users of the genpd provider interface, which are
sprinkled across various subsystems. To release some burden from the
soc maintainers (Arnd Bergmann, etc) in particular, but also to gain a
better overall view of what goes on in the area, I will help out with
maintenance"
[ I find the "genpd" name singularly uninformative, so we'll probably
end up moving this driver subsystem somewhere else, but that's still
being discussed - Linus ]
* tag 'genpd-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (30 commits)
genpd: ti: Use for_each_node_with_property() simplify code logic
genpd: Explicitly include correct DT includes
genpd: imx: scu-pd: initialize is_off according to HW state
genpd: imx: scu-pd: Suppress bind attrs
genpd: imx: scu-pd: do not power off console if no_console_suspend
genpd: imx: scu-pd: add more PDs
genpd: imx: scu-pd: enlarge PD range
genpd: imx: relocate scu-pd under genpd
MAINTAINERS: adjust file entry in STARFIVE JH71XX PMU CONTROLLER DRIVER
genpd: Makefile: build imx
genpd: move owl-sps-helper.c from drivers/soc
soc: starfive: remove stale Makefile entry
ARM: ux500: Move power-domain driver to the genpd dir
ARM: ux500: Convert power-domain code into a regular platform driver
soc: xilinx: Move power-domain driver to the genpd dir
soc: ti: Mover power-domain drivers to the genpd dir
soc: tegra: Move powergate-bpmp driver to the genpd dir
soc: sunxi: Move power-domain driver to the genpd dir
soc: starfive: Move the power-domain driver to the genpd dir
soc: samsung: Move power-domain driver to the genpd dir
...
Diffstat (limited to 'drivers/genpd/renesas/r8a774e1-sysc.c')
-rw-r--r-- | drivers/genpd/renesas/r8a774e1-sysc.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/genpd/renesas/r8a774e1-sysc.c b/drivers/genpd/renesas/r8a774e1-sysc.c new file mode 100644 index 000000000000..18449f746455 --- /dev/null +++ b/drivers/genpd/renesas/r8a774e1-sysc.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2H System Controller + * Copyright (C) 2020 Renesas Electronics Corp. + * + * Based on Renesas R-Car H3 System Controller + * Copyright (C) 2016-2017 Glider bvba + */ + +#include <linux/kernel.h> + +#include <dt-bindings/power/r8a774e1-sysc.h> + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a774e1_areas[] __initconst = { + { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, + { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "ca53-cpu3", 0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "a3vp", 0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON }, + { "a3vc", 0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON }, + { "a2vc1", 0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC }, + { "3dg-a", 0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON }, + { "3dg-b", 0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A }, + { "3dg-c", 0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B }, + { "3dg-d", 0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C }, + { "3dg-e", 0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D }, +}; + +const struct rcar_sysc_info r8a774e1_sysc_info __initconst = { + .areas = r8a774e1_areas, + .num_areas = ARRAY_SIZE(r8a774e1_areas), + .extmask_offs = 0x2f8, + .extmask_val = BIT(0), +}; |