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authorHawking Zhang <Hawking.Zhang@amd.com>2021-06-07 08:22:08 +0300
committerAlex Deucher <alexander.deucher@amd.com>2021-06-11 23:06:21 +0300
commit3a07101b0405c6137babd5f50ca6bdf2696d91c9 (patch)
tree52d57576401d9f5f0d838752139fd61db3455914 /drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
parent8e6e054da6c72210966c82f7d3e7a3d014bd0b39 (diff)
downloadlinux-3a07101b0405c6137babd5f50ca6bdf2696d91c9.tar.xz
drm/amdgpu: disable DRAM memory training when GECC is enabled
GECC and G6 mem training are mutually exclusive functionalities. VBIOS/PSP will set the flag (BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in runtime database to indicate whether dram memory training need to be disabled or not. For Navi1x families, two stage mem training is always enabled. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 45b27c9eb892..3030ec24eb3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -225,6 +225,7 @@ struct psp_memory_training_context {
enum psp_memory_training_init_flag init;
u32 training_cnt;
+ bool enable_mem_training;
};
/** PSP runtime DB **/