diff options
| author | Likun Gao <Likun.Gao@amd.com> | 2022-04-13 00:00:11 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-05-04 17:43:54 +0300 |
| commit | 14ab29241817582e1b92c29ccd738354b2d3241b (patch) | |
| tree | a6d8a1bcdd26566b71cf607a35efe0f2da045adb /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |
| parent | 8e070831d3f814013796a32d1588447592cd589f (diff) | |
| download | linux-14ab29241817582e1b92c29ccd738354b2d3241b.tar.xz | |
drm/amdgpu: support RS64 CP fw front door load
Support to load RS64 CP firmware front door load.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index ddef79820f87..27e503982240 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -672,6 +672,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, { const struct common_firmware_header *header = NULL; const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; + const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; const struct mes_firmware_header_v1_0 *mes_hdr = NULL; @@ -690,6 +691,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, header = (const struct common_firmware_header *)ucode->fw->data; cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; @@ -802,6 +804,61 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); break; + case AMDGPU_UCODE_ID_CP_RS64_PFP: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_ME: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; default: ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); ucode_addr = (u8 *)ucode->fw->data + |