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authorSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>2023-06-30 13:43:55 +0300
committerAlex Deucher <alexander.deucher@amd.com>2023-07-10 16:02:36 +0300
commit0e2b8507c446e24a76e403e0845c49cd8d86862c (patch)
tree1f022628fe3009030d1425fe3765f8e9486e3ce6 /drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
parent67769b7cdd7e1b20059ee19a8e906b1854f9b467 (diff)
downloadlinux-0e2b8507c446e24a76e403e0845c49cd8d86862c.tar.xz
drm/amdgpu: Fix warnings in gfxhub_v2_0.c
Fix the below checkpatch warnings: WARNING: static const char * array should probably be static const char * const +static const char *gfxhub_client_ids[] = { WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + unsigned i; WARNING: Missing a blank line after declarations + u32 tmp; + tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index f173a61c6c15..a041c6c970e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -31,7 +31,7 @@
#include "soc15_common.h"
-static const char *gfxhub_client_ids[] = {
+static const char * const gfxhub_client_ids[] = {
"CB/DB",
"Reserved",
"GE1",
@@ -332,7 +332,7 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
- unsigned i;
+ unsigned int i;
for (i = 0 ; i < 18; ++i) {
WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
@@ -393,6 +393,7 @@ static void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
bool value)
{
u32 tmp;
+
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);