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| author | Likun Gao <Likun.Gao@amd.com> | 2019-06-16 17:37:56 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-06-03 20:52:02 +0300 |
| commit | 757b3af8ecb42414f39ea7996107e8e2b635d7d0 (patch) | |
| tree | fd83ce7a16acda36e129acfe1e03ba12a3015119 /drivers/gpu/drm/amd/amdgpu/navi10_ih.c | |
| parent | 0b3df16b5abc441e39a1ed087115c879dfe23fdf (diff) | |
| download | linux-757b3af8ecb42414f39ea7996107e8e2b635d7d0.tar.xz | |
drm/amdgpu: add ih ip block for sienna_cichlid
Update IH handling for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/navi10_ih.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index f97857ed3c7e..471dc82fd1aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -34,6 +34,9 @@ #define MAX_REARM_RETRY 10 +#define mmIH_CHICKEN_Sienna_Cichlid 0x018d +#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 + static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); /** @@ -265,10 +268,20 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { if (ih->use_bus_addr) { - ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); - ih_chicken = REG_SET_FIELD(ih_chicken, - IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); - WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); + switch (adev->asic_type) { + case CHIP_SIENNA_CICHLID: + ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); + ih_chicken = REG_SET_FIELD(ih_chicken, + IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); + WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); + break; + default: + ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); + ih_chicken = REG_SET_FIELD(ih_chicken, + IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); + WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); + break; + } } } |