diff options
author | Yifan Zha <Yifan.Zha@amd.com> | 2022-08-17 13:44:14 +0300 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2022-09-01 22:11:47 +0300 |
commit | 08c8442c4a032194d6956a266810bf109cdfc138 (patch) | |
tree | 308cc5458f1c6c67ed946e08d7ab864cb0d49f45 /drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | |
parent | 40ad3e545b3da75f107450d32bcad8346fce5dcc (diff) | |
download | linux-08c8442c4a032194d6956a266810bf109cdfc138.tar.xz |
drm/amdgpu: Skip program SDMA0_SEM_WAIT_FAIL_TIMER_CNTL under SRIOV VF
[Why]
As SDMA0_SEM_WAIT_FAIL_TIMER_CNTL is a PF-only register,
L1 would block this register for VF access.
[How]
VF do not program it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index fb31dc911cd7..7ae572a08cb3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -560,7 +560,8 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) for (i = 0; i < adev->sdma.num_instances; i++) { ring = &adev->sdma.instance[i].ring; - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + if (!amdgpu_sriov_vf(adev)) + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); /* Set ring buffer size in dwords */ rb_bufsz = order_base_2(ring->ring_size / 4); |