diff options
| author | Dennis Li <Dennis.Li@amd.com> | 2021-01-26 05:50:41 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-24 05:59:48 +0300 |
| commit | 22616eb5c9b29fca2361d5bd8339efafddee7809 (patch) | |
| tree | 09c187b61f62139176640f75c241ec1c4fb4495b /drivers/gpu/drm/amd/amdgpu/soc15.h | |
| parent | 5217811e74d3b9b6d830476ab8419bbe3d42596e (diff) | |
| download | linux-22616eb5c9b29fca2361d5bd8339efafddee7809.tar.xz | |
drm/amdgpu: add ras support for gfx of aldebaran
add edc counter/status reset and query functions for gfx block of
aldebaran.
v2: change to clear edc counter explicitly
aldebaran hardware will not clear edc counter after driver reading them,
so driver should clear them explicitly.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index 0e37f4ce8364..ea0469e45b9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -49,6 +49,13 @@ struct soc15_reg_rlcg { u32 reg; }; +struct soc15_reg { + uint32_t hwip; + uint32_t inst; + uint32_t seg; + uint32_t reg_offset; +}; + struct soc15_reg_entry { uint32_t hwip; uint32_t inst; @@ -88,6 +95,10 @@ struct soc15_ras_field_entry { #define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT +#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift) + +#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL(val, entry.field##_count_mask, entry.field##_count_shift) + void soc15_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); void soc15_set_virt_ops(struct amdgpu_device *adev); |