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authorRex Zhu <Rex.Zhu@amd.com>2016-08-18 08:02:46 +0300
committerAlex Deucher <alexander.deucher@amd.com>2016-08-25 19:22:24 +0300
commitcbb2fe8e967dbc88f236aa7da1bb3f79b61022f9 (patch)
tree6d2e1c158cd3b6367e09bda6e9ac2280ce9f4388 /drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
parent0174df4e664dfc481b6ee3f9f4528c0b727b6fb0 (diff)
downloadlinux-cbb2fe8e967dbc88f236aa7da1bb3f79b61022f9.tar.xz
drm/amd/powerplay: add bypass mode for vce 2.0.
fix issue after vce encode, the eclk stay high. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vce_v2_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c21
1 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 3fcc33f9ae70..58af0da387b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -30,10 +30,10 @@
#include "amdgpu.h"
#include "amdgpu_vce.h"
#include "cikd.h"
-
#include "vce/vce_2_0_d.h"
#include "vce/vce_2_0_sh_mask.h"
-
+#include "smu/smu_7_0_1_d.h"
+#include "smu/smu_7_0_1_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
@@ -539,11 +539,28 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
+static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
+{
+ u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
+
+ if (enable)
+ tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
+ else
+ tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
+
+ WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
+}
+
+
static int vce_v2_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
bool gate = false;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+
+
+ vce_v2_0_set_bypass_mode(adev, enable);
if (state == AMD_CG_STATE_GATE)
gate = true;