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| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2023-03-02 09:23:47 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 16:58:17 +0300 |
| commit | 6d39fa3fc802e511241898a6890a9b2ec7f958e3 (patch) | |
| tree | f29ed2e5cf4315bde4dedce8b8511b9686cdd1e6 /drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | |
| parent | 5e1e227fb7cbea2624b4b9375a9b888d02fed4f5 (diff) | |
| download | linux-6d39fa3fc802e511241898a6890a9b2ec7f958e3.tar.xz | |
drm/amdgpu: Add reset_ras_error_count for vcn v4_0_3
Add reset_ras_error_count callback for vcn v4_0_3.
It will be used to reset vcn ras error count.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index e5037d6f884b..e8933039bcd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1466,3 +1466,25 @@ static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, for (i = 0; i < adev->vcn.num_vcn_inst; i++) vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); } + +static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, + uint32_t vcn_inst) +{ + amdgpu_ras_inst_reset_ras_error_count(adev, + vcn_v4_0_3_ue_reg_list, + ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), + GET_INST(VCN, vcn_inst)); +} + +static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) +{ + uint32_t i; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { + dev_warn(adev->dev, "VCN RAS is not supported\n"); + return; + } + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + vcn_v4_0_3_inst_reset_ras_error_count(adev, i); +} |