diff options
| author | Alex Xie <AlexBin.Xie@amd.com> | 2017-03-30 20:30:00 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-03-30 22:16:00 +0300 |
| commit | 60508d3df2d2052881190ac82802a12cabcef53c (patch) | |
| tree | 94f7d4526fe19a32643308d6e00d0fc5442af277 /drivers/gpu/drm/amd/amdgpu/vega10_ih.c | |
| parent | c7217b2af83e85dd6053ff13dc4ac2d24d85b97c (diff) | |
| download | linux-60508d3df2d2052881190ac82802a12cabcef53c.tar.xz | |
drm/amdgpu: Fix 32bit x86 compilation warning
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:187:2: warning: right shift count >= width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:173:2: warning: right shift count >= width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/vega10_ih.c:106:3: warning: right shift count >= width of type [enabled by default]
v2: Add a space between "&" and "0xff"
Reported by: kbuild-all@01.org
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vega10_ih.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 23371e1c09ef..071f56e439bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -103,7 +103,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ if (adev->irq.ih.use_bus_addr) { WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.rb_dma_addr >> 40) &0xff); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); } else { WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8); |