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| author | Laurent Morichetti <laurent.morichetti@amd.com> | 2020-07-07 02:13:40 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-27 23:20:47 +0300 |
| commit | 0a5baee415000a3e18730ac98e19d046c3cebbe6 (patch) | |
| tree | 501d51660b92be347fefd81a18588c0acc170ef4 /drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | |
| parent | 26cfd12b5e24993ac943ac37044128fe33b3ed94 (diff) | |
| download | linux-0a5baee415000a3e18730ac98e19d046c3cebbe6.tar.xz | |
drm/amdkfd: Unify gfx9/gfx10 context save area layouts
Add some padding before the MODE register in the HWREGs block to
preserve the same layout as gfx9. This simplifies implementation of a
user-mode debugger.
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm')
| -rw-r--r-- | drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm index 5b220f2a7501..4569db452160 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm @@ -407,6 +407,7 @@ L_SAVE_HWREG: // Not used on Sienna_Cichlid but keep layout same for debugger. write_hwreg_to_mem(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset) + s_add_u32 s_save_mem_offset, s_save_mem_offset, 4 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) @@ -912,6 +913,7 @@ L_RESTORE_HWREG: read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset) + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 4 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) s_waitcnt lgkmcnt(0) |