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authorCharlene Liu <Charlene.Liu@amd.com>2020-05-22 18:29:36 +0300
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 08:59:20 +0300
commit2166d9fb6e660fc17d37dc833cd691bc7ee0b4db (patch)
tree5fc8312cd327cda923bbcda7d671b8df7fbe4a89 /drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
parent92bfc4a196977d75da15f7544fd538e71684ca39 (diff)
downloadlinux-2166d9fb6e660fc17d37dc833cd691bc7ee0b4db.tar.xz
drm/amd/display: update audio wall clock programming
[why] for audio on real TV issue. [how] -add wall clock programming for DPREF based when Pixel clock is done by DP DTO. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_audio.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_audio.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 5a35495bc11d..408046579712 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -140,6 +140,8 @@ static void check_audio_bandwidth_hdmi(
bool limit_freq_to_88_2_khz = false;
bool limit_freq_to_96_khz = false;
bool limit_freq_to_174_4_khz = false;
+ if (!crtc_info)
+ return;
/* For two channels supported return whatever sink support,unmodified*/
if (channel_count > 2) {
@@ -784,7 +786,7 @@ void dce_aud_wall_dto_setup(
struct azalia_clock_info clock_info = { 0 };
- if (dc_is_hdmi_signal(signal)) {
+ if (dc_is_hdmi_tmds_signal(signal)) {
uint32_t src_sel;
/*DTO0 Programming goal: