diff options
| author | Charlene Liu <Charlene.Liu@amd.com> | 2023-03-09 23:03:50 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-03-22 07:59:52 +0300 |
| commit | a36f72547e0eb623912957aeb68465e3c9f7effe (patch) | |
| tree | 3419178fd798b276945cb2202ef91bc3256d2d2f /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | a8b537605e22bfe277e666727fa0e9e01f2c729b (diff) | |
| download | linux-a36f72547e0eb623912957aeb68465e3c9f7effe.tar.xz | |
drm/amd/display: Add CRC and DMUB test support
[Why & How]
- Add CRC for test support
- Add params to allow control into to DMUB.
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index 0b37bb0e184b..db766689af58 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -161,10 +161,20 @@ struct dcn_optc_registers { uint32_t OTG_CRC_CNTL2; uint32_t OTG_CRC0_DATA_RG; uint32_t OTG_CRC0_DATA_B; + uint32_t OTG_CRC1_DATA_B; + uint32_t OTG_CRC2_DATA_B; + uint32_t OTG_CRC3_DATA_B; + uint32_t OTG_CRC1_DATA_RG; + uint32_t OTG_CRC2_DATA_RG; + uint32_t OTG_CRC3_DATA_RG; uint32_t OTG_CRC0_WINDOWA_X_CONTROL; uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; uint32_t OTG_CRC0_WINDOWB_X_CONTROL; uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; + uint32_t OTG_CRC1_WINDOWA_X_CONTROL; + uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; + uint32_t OTG_CRC1_WINDOWB_X_CONTROL; + uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; uint32_t GSL_SOURCE_SELECT; uint32_t DWB_SOURCE_SELECT; uint32_t OTG_DSC_START_POSITION; @@ -464,6 +474,15 @@ struct dcn_optc_registers { type CRC0_R_CR;\ type CRC0_G_Y;\ type CRC0_B_CB;\ + type CRC1_R_CR;\ + type CRC1_G_Y;\ + type CRC1_B_CB;\ + type CRC2_R_CR;\ + type CRC2_G_Y;\ + type CRC2_B_CB;\ + type CRC3_R_CR;\ + type CRC3_G_Y;\ + type CRC3_B_CB;\ type OTG_CRC0_WINDOWA_X_START;\ type OTG_CRC0_WINDOWA_X_END;\ type OTG_CRC0_WINDOWA_Y_START;\ @@ -472,6 +491,15 @@ struct dcn_optc_registers { type OTG_CRC0_WINDOWB_X_END;\ type OTG_CRC0_WINDOWB_Y_START;\ type OTG_CRC0_WINDOWB_Y_END;\ + type OTG_CRC_WINDOW_DB_EN;\ + type OTG_CRC1_WINDOWA_X_START;\ + type OTG_CRC1_WINDOWA_X_END;\ + type OTG_CRC1_WINDOWA_Y_START;\ + type OTG_CRC1_WINDOWA_Y_END;\ + type OTG_CRC1_WINDOWB_X_START;\ + type OTG_CRC1_WINDOWB_X_END;\ + type OTG_CRC1_WINDOWB_Y_START;\ + type OTG_CRC1_WINDOWB_Y_END;\ type GSL0_READY_SOURCE_SEL;\ type GSL1_READY_SOURCE_SEL;\ type GSL2_READY_SOURCE_SEL;\ @@ -525,6 +553,7 @@ struct dcn_optc_registers { #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; + struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) |