diff options
author | Roman Li <Roman.Li@amd.com> | 2020-09-29 18:21:58 +0300 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-05 22:15:56 +0300 |
commit | 3a83e4e64bb1522ddac67ffc787d1c38291e1a65 (patch) | |
tree | 907efd005ca3c474afd17acae74f53aec1a8836e /drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | |
parent | ac0dc4c5a0760c9a9437d5864c277d9d2554a6ec (diff) | |
download | linux-3a83e4e64bb1522ddac67ffc787d1c38291e1a65.tar.xz |
drm/amd/display: Add dcn3.01 support to DC (v2)
Update dc for vangogh support.
v2: fix compilation without DCN 301 set.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dm_pp_smu.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h index 3586934df25f..e05273d4739d 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h @@ -278,14 +278,38 @@ struct pp_smu_funcs_rn { enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp, struct dpm_clocks *clock_table); }; +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +struct pp_smu_funcs_vgh { + struct pp_smu pp_smu; + /* + * reader and writer WM's are sent together as part of one table + * + * PPSMC_MSG_SetDriverDramAddrHigh + * PPSMC_MSG_SetDriverDramAddrLow + * PPSMC_MSG_TransferTableDram2Smu + * + */ + // TODO: Check whether this is moved to DAL, and remove as needed + enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp, + struct pp_smu_wm_range_sets *ranges); + + // TODO: Check whether this is moved to DAL, and remove as needed + enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp, + struct dpm_clocks *clock_table); + + enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp); +}; +#endif struct pp_smu_funcs { struct pp_smu ctx; union { struct pp_smu_funcs_rv rv_funcs; struct pp_smu_funcs_nv nv_funcs; struct pp_smu_funcs_rn rn_funcs; - +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + struct pp_smu_funcs_vgh vgh_funcs; +#endif }; }; |