diff options
author | Tony Cheng <tony.cheng@amd.com> | 2017-08-13 20:50:52 +0300 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-27 01:16:46 +0300 |
commit | a185048ca88ce143f980f2b819f034cfc09a5377 (patch) | |
tree | eb611070959085f5a1fbcf1f2f9201707a08d559 /drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | |
parent | 1e8635ea0ea370bf4f0f2b2f1b3eb61474dd962a (diff) | |
download | linux-a185048ca88ce143f980f2b819f034cfc09a5377.tar.xz |
drm/amd/display: refactor pplib/smu communication
new per SoC interface instead legacy interface with lots of un-used
field that only cause confusion
model pp_smu like one of our HW objects with func_ptr interface
to call into it. struct pp_smu as handle to call pp/smu
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dm_pp_smu.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h new file mode 100644 index 000000000000..bbfa83252fc1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h @@ -0,0 +1,131 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DM_PP_SMU_IF__H +#define DM_PP_SMU_IF__H + +/* + * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC + */ + + +struct pp_smu { + struct dc_context *ctx; +}; + +enum wm_set_id { + WM_A, + WM_B, + WM_C, + WM_D, + WM_COUNT, +}; + +struct pp_smu_wm_set_range { + enum wm_set_id wm_inst; + uint32_t min_fill_clk_khz; + uint32_t max_fill_clk_khz; + uint32_t min_drain_clk_khz; + uint32_t max_drain_clk_khz; +}; + +struct pp_smu_wm_range_sets { + uint32_t num_reader_wm_sets; + struct pp_smu_wm_set_range reader_wm_sets[WM_COUNT]; + + uint32_t num_writer_wm_sets; + struct pp_smu_wm_set_range writer_wm_sets[WM_COUNT]; +}; + +struct pp_smu_display_requirement_rv { + /* PPSMC_MSG_SetDisplayCount: count + * 0 triggers S0i2 optimization + */ + unsigned int display_count; + + /* PPSMC_MSG_SetHardMinFclkByFreq: khz + * FCLK will vary with DPM, but never below requested hard min + */ + unsigned int hard_min_fclk_khz; + + /* PPSMC_MSG_SetHardMinDcefclkByFreq: khz + * fixed clock at requested freq, either from FCH bypass or DFS + */ + unsigned int hard_min_dcefclk_khz; + + /* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz + * when DF is in cstate, dcf clock is further divided down + * to just above given frequency + */ + unsigned int min_deep_sleep_dcefclk_mhz; +}; + +struct pp_smu_funcs_rv { + struct pp_smu pp_smu; + + void (*set_display_requirement)(struct pp_smu *pp, + struct pp_smu_display_requirement_rv *req); + + /* which SMU message? are reader and writer WM separate SMU msg? */ + void (*set_wm_ranges)(struct pp_smu *pp, + struct pp_smu_wm_range_sets *ranges); + +}; + +#if 0 +struct pp_smu_funcs_rv { + + /* PPSMC_MSG_SetDisplayCount + * 0 triggers S0i2 optimization + */ + void (*set_display_count)(struct pp_smu *pp, int count); + + /* PPSMC_MSG_SetHardMinFclkByFreq + * FCLK will vary with DPM, but never below requested hard min + */ + void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz); + + /* PPSMC_MSG_SetHardMinDcefclkByFreq + * fixed clock at requested freq, either from FCH bypass or DFS + */ + void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz); + + /* PPSMC_MSG_SetMinDeepSleepDcefclk + * when DF is in cstate, dcf clock is further divided down + * to just above given frequency + */ + void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz); + + /* todo: aesthetic + * watermark range table + */ + + /* todo: functional/feature + * PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB + */ +}; +#endif + +#endif /* DM_PP_SMU_IF__H */ |