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authorHersen Wu <hersenxs.wu@amd.com>2019-10-15 19:47:31 +0300
committerAlex Deucher <alexander.deucher@amd.com>2019-10-15 22:51:25 +0300
commite70bd049d00729b6c632c8ddd921bc3c5afaf19b (patch)
tree0de1294ff61621031dac30efc1ca774bc4d630f4 /drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
parent71a0df4be65bfa5b0ccfe10d9c99fc2d516d8083 (diff)
downloadlinux-e70bd049d00729b6c632c8ddd921bc3c5afaf19b.tar.xz
drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, there is build error. struct dpm_clocks shoud not be guarded. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dm_pp_smu.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dm_pp_smu.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 24d65dbbd749..ef7df9ef6d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -249,8 +249,6 @@ struct pp_smu_funcs_nv {
};
#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
-
#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
@@ -288,7 +286,6 @@ struct pp_smu_funcs_rn {
enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
struct dpm_clocks *clock_table);
};
-#endif
struct pp_smu_funcs {
struct pp_smu ctx;