diff options
| author | Charlene Liu <charlene.liu@amd.com> | 2023-08-30 04:08:38 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-09 23:51:06 +0300 |
| commit | 0e56de91edd0b81e2c8df98413e68bed4ef13706 (patch) | |
| tree | ca6040ebd4325ca638254d2efed5e8169f5ce957 /drivers/gpu/drm/amd/display/dc/dml2 | |
| parent | 969fe903ee2ea8e6a7781608ca2ee72d9b748c00 (diff) | |
| download | linux-0e56de91edd0b81e2c8df98413e68bed4ef13706.tar.xz | |
drm/amd/display: correct dml2 input and dlg_refclk
dc->dml2_options.use_native_pstate_optimization flag will make driver
use dcn32 legacy_svp_drr related tuning. Set this to false fixed the
stutter underflow issue also based on HW suggest disable ODM by default
and let DML choose it.
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml2')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c index 552d5cffce2d..11c131f6cf26 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c @@ -67,8 +67,12 @@ static void map_hw_resources(struct dml2_context *dml2, in_out_display_cfg->hw.DPPPerSurface[i] = mode_support_info->DPPPerSurface[i]; in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i]; - in_out_display_cfg->hw.DLGRefClkFreqMHz = 50; - + in_out_display_cfg->hw.DLGRefClkFreqMHz = 24; + if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && + dml2->v20.dml_core_ctx.project != dml_project_dcn351) { + /*dGPU default as 50Mhz*/ + in_out_display_cfg->hw.DLGRefClkFreqMHz = 50; + } for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) { dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i]; dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true; |