diff options
| author | Sung Joon Kim <sungkim@amd.com> | 2023-09-29 19:12:47 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-27 01:57:15 +0300 |
| commit | d591284288c29f04e52ae4f3d605e2f39c3e316c (patch) | |
| tree | d46674f745ac712311fee096c24f5b9dff54204a /drivers/gpu/drm/amd/display/dc/hwss | |
| parent | d5f9a92bd1e234b8a7cf6f350b5bc0169221ae59 (diff) | |
| download | linux-d591284288c29f04e52ae4f3d605e2f39c3e316c.tar.xz | |
drm/amd/display: Add a check for idle power optimization
[why]
Need a helper function to check idle power is allowed
so that dc doesn't access any registers that are power-gated.
[how]
Implement helper function to check idle power optimization.
Enable a hook to check if detection is allowed.
V2:
Add function hooks for set and get idle states.
Check if function hook was properly initialized.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Nicholas Choi <nicholas.choi@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index a22cd2aee286..97798cee876e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -585,7 +585,9 @@ void dcn31_reset_hw_ctx_wrap( struct clock_source *old_clk = pipe_ctx_old->clock_source; /* Reset pipe which is seamless boot stream. */ - if (!pipe_ctx_old->plane_state) { + if (!pipe_ctx_old->plane_state && + dc->res_pool->hubbub->funcs->program_det_size && + dc->res_pool->hubbub->funcs->wait_for_det_apply) { dc->res_pool->hubbub->funcs->program_det_size( dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0); /* Wait det size changed. */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 8f717db01f85..ece806a63d8d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -629,12 +629,8 @@ void dcn35_power_down_on_boot(struct dc *dc) if (dc->clk_mgr->funcs->set_low_power_state) dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr); - if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) { - if (!dc->idle_optimizations_allowed) { - dc_dmub_srv_notify_idle(dc, true); - dc->idle_optimizations_allowed = true; - } - } + if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) + dc_allow_idle_optimizations(dc, true); } bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index d45302035e3f..c43d1f6c2a06 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -418,6 +418,8 @@ struct hw_sequencer_funcs { struct pg_block_update *update_state, bool power_on); void (*root_clock_control)(struct dc *dc, struct pg_block_update *update_state, bool power_on); + void (*set_idle_state)(const struct dc *dc, bool allow_idle); + uint32_t (*get_idle_state)(const struct dc *dc); bool (*is_pipe_topology_transition_seamless)(struct dc *dc, const struct dc_state *cur_ctx, |