drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu instead of dce_clocks

Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 0 insertions, 101 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 7307f96c7679..d330d38aff16 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -47,43 +47,6 @@ struct encoder_feature_support {
 	bool ycbcr420_supported;
 };
 
-enum physical_phy_id {
-	PHYLD_0,
-	PHYLD_1,
-	PHYLD_2,
-	PHYLD_3,
-	PHYLD_4,
-	PHYLD_5,
-	PHYLD_6,
-	PHYLD_7,
-	PHYLD_8,
-	PHYLD_9,
-	PHYLD_COUNT,
-	PHYLD_UNKNOWN = (-1L)
-};
-
-enum phy_type {
-	PHY_TYPE_UNKNOWN  = 1,
-	PHY_TYPE_PCIE_PHY = 2,
-	PHY_TYPE_UNIPHY = 3,
-};
-
-union dmcu_psr_level {
-	struct {
-		unsigned int SKIP_CRC:1;
-		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
-		unsigned int SKIP_PHY_POWER_DOWN:1;
-		unsigned int SKIP_AUX_ACK_CHECK:1;
-		unsigned int SKIP_CRTC_DISABLE:1;
-		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
-		unsigned int SKIP_SMU_NOTIFICATION:1;
-		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
-		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
-		unsigned int RESERVED:23;
-	} bits;
-	unsigned int u32all;
-};
-
 union dpcd_psr_configuration {
 	struct {
 		unsigned char ENABLE                    : 1;
@@ -116,70 +79,6 @@ union psr_sink_psr_status {
 	unsigned char raw;
 };
 
-struct psr_context {
-	/* ddc line */
-	enum channel_id channel;
-	/* Transmitter id */
-	enum transmitter transmitterId;
-	/* Engine Id is used for Dig Be source select */
-	enum engine_id engineId;
-	/* Controller Id used for Dig Fe source select */
-	enum controller_id controllerId;
-	/* Pcie or Uniphy */
-	enum phy_type phyType;
-	/* Physical PHY Id used by SMU interpretation */
-	enum physical_phy_id smuPhyId;
-	/* Vertical total pixels from crtc timing.
-	 * This is used for static screen detection.
-	 * ie. If we want to detect half a frame,
-	 * we use this to determine the hyst lines.
-	 */
-	unsigned int crtcTimingVerticalTotal;
-	/* PSR supported from panel capabilities and
-	 * current display configuration
-	 */
-	bool psrSupportedDisplayConfig;
-	/* Whether fast link training is supported by the panel */
-	bool psrExitLinkTrainingRequired;
-	/* If RFB setup time is greater than the total VBLANK time,
-	 * it is not possible for the sink to capture the video frame
-	 * in the same frame the SDP is sent. In this case,
-	 * the frame capture indication bit should be set and an extra
-	 * static frame should be transmitted to the sink.
-	 */
-	bool psrFrameCaptureIndicationReq;
-	/* Set the last possible line SDP may be transmitted without violating
-	 * the RFB setup time or entering the active video frame.
-	 */
-	unsigned int sdpTransmitLineNumDeadline;
-	/* The VSync rate in Hz used to calculate the
-	 * step size for smooth brightness feature
-	 */
-	unsigned int vsyncRateHz;
-	unsigned int skipPsrWaitForPllLock;
-	unsigned int numberOfControllers;
-	/* Unused, for future use. To indicate that first changed frame from
-	 * state3 shouldn't result in psr_inactive, but rather to perform
-	 * an automatic single frame rfb_update.
-	 */
-	bool rfb_update_auto_en;
-	/* Number of frame before entering static screen */
-	unsigned int timehyst_frames;
-	/* Partial frames before entering static screen */
-	unsigned int hyst_lines;
-	/* # of repeated AUX transaction attempts to make before
-	 * indicating failure to the driver
-	 */
-	unsigned int aux_repeats;
-	/* Controls hw blocks to power down during PSR active state */
-	union dmcu_psr_level psr_level;
-	/* Controls additional delay after remote frame capture before
-	 * continuing powerd own
-	 */
-	unsigned int frame_delay;
-};
-
-
 struct link_encoder {
 	const struct link_encoder_funcs *funcs;
 	int32_t aux_channel_offset;