diff options
author | Lewis Huang <Lewis.Huang@amd.com> | 2019-09-05 10:33:58 +0300 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-11 03:32:03 +0300 |
commit | f537d474df15393ad25721f5203ce16ed3596d66 (patch) | |
tree | 3ea2943d295e52b149889bdc9ff0b5c619fbc27c /drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | |
parent | d832fc3b182045185e3dd92e20ac31c84be68da7 (diff) | |
download | linux-f537d474df15393ad25721f5203ce16ed3596d66.tar.xz |
drm/amd/display: check phy dpalt lane count config
[Why]
Type-c PHY config is not align with dpcd lane count.
When those values didn't match, it cause driver do
link training with 4 lane but phy only can output 2 lane.
The link trainig always fail.
[How]
1. Modify get_max_link_cap function. According DPALT_DP4
to update max lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index abb4e4237fb6..b21909216fb6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -184,6 +184,10 @@ struct link_encoder_funcs { bool (*fec_is_active)(struct link_encoder *enc); #endif bool (*is_in_alt_mode) (struct link_encoder *enc); + + void (*get_max_link_cap)(struct link_encoder *enc, + struct dc_link_settings *link_settings); + enum signal_type (*get_dig_mode)( struct link_encoder *enc); }; |