diff options
| author | Felipe Clark <felipe.clark@amd.com> | 2021-03-07 21:27:30 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-15 04:38:41 +0300 |
| commit | c2fbe663ec4f991832d67f936d3941f781884156 (patch) | |
| tree | 5c07defd0735bac8e62f7a7ee775bd7e3c1e9bac /drivers/gpu/drm/amd/display/modules | |
| parent | a34136a3b3526369e1b3e678590e3760e7653f0f (diff) | |
| download | linux-c2fbe663ec4f991832d67f936d3941f781884156.tar.xz | |
drm/amd/display: Firmware assisted MCLK switch and FS
[WHY]
Memory clock switching has great potential for power savings.
[HOW]
The driver code was modified to notify the DMCUB firmware that it should
stretch the vertical blank of frames when a memory clock switch is about
to start so that no blackouts happen on the screen due to unavailability
of the frame buffer.
The driver logic to determine when such firmware assisted strategy can
be initiated is also implemented and consists on checking prerequisites
of the feature.
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Felipe Clark <felipe.clark@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules')
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 03fa63d56fa6..aa121d45d9b8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1374,6 +1374,11 @@ unsigned long long mod_freesync_calc_field_rate_from_timing( return field_rate_in_uhz; } +bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, struct dc_stream_state *const pStream) +{ + return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED); +} + bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, uint32_t max_refresh_cap_in_uhz, uint32_t nominal_field_rate_in_uhz) diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index cf6bc9446244..62e326dd29a8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -194,4 +194,8 @@ unsigned int mod_freesync_calc_v_total_from_refresh( const struct dc_stream_state *stream, unsigned int refresh_in_uhz); +// Returns true when FreeSync is supported and enabled (even if it is inactive) +bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, + struct dc_stream_state *const pStream); + #endif |