diff options
author | Feifei Xu <Feifei.Xu@amd.com> | 2017-11-24 07:31:36 +0300 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 20:48:22 +0300 |
commit | fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd (patch) | |
tree | a36bcf5723014f3d98b5d5bc5c56d5641be7911c /drivers/gpu/drm/amd | |
parent | 8af7454e7c6b20cd8d130f08c443d1e76033d0ca (diff) | |
download | linux-fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd.tar.xz |
drm/amd/include:cleanup vega10 header files.
Remove asic_reg/vega10 folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
32 files changed, 36 insertions, 36 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index df218df332b3..c22c73f458bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -35,7 +35,7 @@ #include "soc15d.h" #include "soc15_common.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/VCN/vcn_1_0_offset.h" /* 1 second timeout */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 35e134df7e07..6c5289ae67be 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -28,10 +28,10 @@ #include "soc15.h" #include "soc15d.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "hdp/hdp_4_0_offset.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 9c93b20bf4ed..f1effadfbaa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -23,11 +23,11 @@ #include "amdgpu.h" #include "gfxhub_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "gc/gc_9_0_default.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index a201efd41279..30eb625a991c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -25,13 +25,13 @@ #include "gmc_v9_0.h" #include "amdgpu_atomfirmware.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "hdp/hdp_4_0_offset.h" #include "hdp/hdp_4_0_sh_mask.h" #include "gc/gc_9_0_sh_mask.h" #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "mmhub/mmhub_1_0_offset.h" #include "athub/athub_1_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index d2268575b098..bd160d8700e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -23,13 +23,13 @@ #include "amdgpu.h" #include "mmhub_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "mmhub/mmhub_1_0_offset.h" #include "mmhub/mmhub_1_0_sh_mask.h" #include "mmhub/mmhub_1_0_default.h" #include "athub/athub_1_0_offset.h" #include "athub/athub_1_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 19327b782124..ad9054e3903c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -22,7 +22,7 @@ */ #include "amdgpu.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index fd9f71e8a2d2..76db711097c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -24,11 +24,11 @@ #include "amdgpu_atombios.h" #include "nbio_v6_1.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "nbio/nbio_6_1_default.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #define smnCPM_CONTROL 0x11180460 #define smnPCIE_CNTL2 0x11180070 diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index f802b973410a..8ddc44b503e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -24,11 +24,11 @@ #include "amdgpu_atombios.h" #include "nbio_v7_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/NBIO/nbio_7_0_default.h" #include "raven1/NBIO/nbio_7_0_offset.h" #include "raven1/NBIO/nbio_7_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 4e20d91d5d50..062cd8af6b19 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -30,7 +30,7 @@ #include "soc15_common.h" #include "psp_v10_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/MP/mp_10_0_offset.h" #include "raven1/GC/gc_9_1_offset.h" #include "raven1/SDMA0/sdma0_4_1_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 7a9832b8ff51..e75a23d858ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -31,7 +31,7 @@ #include "soc15_common.h" #include "psp_v3_1.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "mp/mp_9_0_offset.h" #include "mp/mp_9_0_sh_mask.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 67b34914679f..a487fa7cb30a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -27,7 +27,7 @@ #include "amdgpu_ucode.h" #include "amdgpu_trace.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "sdma0/sdma0_4_0_offset.h" #include "sdma0/sdma0_4_0_sh_mask.h" #include "sdma1/sdma1_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 85d7e6f1a3c5..f134ca0c093c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -34,7 +34,7 @@ #include "atom.h" #include "amd_pcie.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index c271c6b4b451..660fa41dc877 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -29,7 +29,7 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "uvd/uvd_7_0_sh_mask.h" #include "vce/vce_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index a6bb51b1322c..d06bafe28c2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -32,7 +32,7 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "vce/vce_4_0_offset.h" #include "vce/vce_4_0_default.h" #include "vce/vce_4_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 061088cca72e..ab92cd71d4c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -28,7 +28,7 @@ #include "soc15d.h" #include "soc15_common.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/VCN/vcn_1_0_offset.h" #include "raven1/VCN/vcn_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 76626786c3fc..ca778cd4e6e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -26,7 +26,7 @@ #include "soc15.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "oss/osssys_4_0_offset.h" #include "oss/osssys_4_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 533f730ff648..1c60b018ad1e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -61,7 +61,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "soc15_common.h" #endif diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 8613ecf06514..75d029742f96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -33,7 +33,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "reg_helper.h" #define CTX \ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 9d64e669ba52..57cd67359567 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -56,7 +56,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "nbio/nbio_6_1_offset.h" #include "reg_helper.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 5ad04d24fd27..0aa60e5727e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -27,7 +27,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "dc_types.h" #include "dc_bios_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9ea100223020..63d05f34db9f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -50,7 +50,7 @@ #include "dcn10_hubp.h" #include "dcn10_hubbub.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c index d8b70d151457..0c2314efb47e 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c @@ -36,7 +36,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #define block HPD #define reg_num 0 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c index 0d0bc440835f..a225b02cc779 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c @@ -35,7 +35,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c index 409763c70ce5..f937b354fdd5 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c @@ -36,7 +36,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #define block HPD #define reg_num 0 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c index 64a6915b846b..75bfe6ae962b 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c @@ -35,7 +35,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 0de53257b865..a401636bf3f8 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -38,7 +38,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index 13b807d8aff8..b5237322ef41 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -38,7 +38,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 8135d7a5f4d6..66d52580e29f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -32,7 +32,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "ivsrcid/ivsrcid_vislands30.h" diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index 74ad24714f6b..8e2dabe08bd0 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -31,7 +31,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "irq_service_dcn10.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h b/drivers/gpu/drm/amd/include/soc15ip.h index 1767db69df7a..1767db69df7a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h +++ b/drivers/gpu/drm/amd/include/soc15ip.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h b/drivers/gpu/drm/amd/include/vega10_enum.h index c14ba65a2415..c14ba65a2415 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h +++ b/drivers/gpu/drm/amd/include/vega10_enum.h diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h index a511611ec7e0..b7ab69e4c254 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h @@ -23,7 +23,7 @@ #ifndef PP_SOC15_H #define PP_SOC15_H -#include "vega10/soc15ip.h" +#include "soc15ip.h" inline static uint32_t soc15_get_register_offset( uint32_t hw_id, |