diff options
| author | Liu Ying <victor.liu@nxp.com> | 2023-10-18 06:52:12 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-10-24 21:35:11 +0300 |
| commit | 93e82bb4de0196c4caeca1d8a6eef67863981d8f (patch) | |
| tree | 3153a6ece8cf54dd8b52e99e0e2ff9004e293950 /drivers/gpu/drm/bridge | |
| parent | 6ae2ff23aa43a0c421cf315c34b105bdfe317f63 (diff) | |
| download | linux-93e82bb4de0196c4caeca1d8a6eef67863981d8f.tar.xz | |
drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode
In order to support burst mode, vendor drivers set lane_mbps higher than
bandwidth through DPI interface. So, calculate horizontal component lane
byte clock cycle(lbcc) based on lane_mbps instead of pixel clock rate for
burst mode.
Fixes: ac87d23694f4 ("drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock rate to calculate lbcc")
Reported-by: Heiko Stübner <heiko@sntech.de>
Closes: https://lore.kernel.org/linux-arm-kernel/5979575.UjTJXf6HLC@diego/T/#u
Tested-by: Heiko Stübner <heiko@sntech.de> # px30 minievb with xinpeng xpp055c272
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231018035212.1778767-1-victor.liu@nxp.com
Diffstat (limited to 'drivers/gpu/drm/bridge')
| -rw-r--r-- | drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 8789eca26188..824fb3c65742 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -774,13 +774,19 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, u32 frac, lbcc, minimum_lbcc; int bpp; - bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); - if (bpp < 0) { - dev_err(dsi->dev, "failed to get bpp\n"); - return 0; - } + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + /* lbcc based on lane_mbps */ + lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; + } else { + /* lbcc based on pixel clock rate */ + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + if (bpp < 0) { + dev_err(dsi->dev, "failed to get bpp\n"); + return 0; + } - lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8); + lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8); + } frac = lbcc % mode->clock; lbcc = lbcc / mode->clock; |