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authorFei Yang <fei.yang@intel.com>2023-05-19 08:11:02 +0300
committerAndi Shyti <andi.shyti@linux.intel.com>2023-05-23 11:15:26 +0300
commit0fbcf57077c47b444e91b9ce8a243e6f7f53693d (patch)
tree514f45fe0273dab47eb1aa6d2bd5ad8b0885bf97 /drivers/gpu/drm/i915/gem/i915_gem_domain.c
parent906bd0fb137ffc361b3ce0d0db07f288db5582ea (diff)
downloadlinux-0fbcf57077c47b444e91b9ce8a243e6f7f53693d.tar.xz
drm/i915/mtl: end support for set caching ioctl
The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. For userspace components needing to fine tune the caching policy for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow them specify caching mode at BO creation time. Signed-off-by: Fei Yang <fei.yang@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230519051103.3404990-2-fei.yang@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gem/i915_gem_domain.c')
-rw-r--r--drivers/gpu/drm/i915/gem/i915_gem_domain.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 05107a6efe45..dfaaa8b66ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -350,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
if (IS_DGFX(i915))
return -ENODEV;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ return -EOPNOTSUPP;
+
switch (args->caching) {
case I915_CACHING_NONE:
level = I915_CACHE_NONE;