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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-08-30 05:50:36 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-08-30 07:56:33 +0300 |
| commit | b244ffa15c8b1aabdc117c0b6008086df7b668b7 (patch) | |
| tree | 973d945998d4ebe9195c839ac266902708c1297e /drivers/gpu/drm/i915/gvt/fb_decoder.h | |
| parent | b2b599fb54f90ae395ddc51f0d49e4f28244a8f8 (diff) | |
| download | linux-b244ffa15c8b1aabdc117c0b6008086df7b668b7.tar.xz | |
drm/i915/gvt: Fix drm_format_mod value for vGPU plane
Physical plane's tiling mode value is given directly as
drm_format_mod for plane query, which is not correct fourcc
code. Fix it by using correct intel tiling fourcc mod definition.
Current qemu seems also doesn't correctly utilize drm_format_mod
for plane object setting. Anyway this is required to fix the usage.
v3: use DRM_FORMAT_MOD_LINEAR, fix comment
v2: Fix missed old 'tiled' use for stride calculation
Fixes: e546e281d33d ("drm/i915/gvt: Dmabuf support for GVT-g")
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Colin Xu <Colin.Xu@intel.com>
Reviewed-by: Colin Xu <Colin.Xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/fb_decoder.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h index cb055f3c81a2..60c155085029 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.h +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h @@ -101,7 +101,7 @@ struct intel_gvt; /* color space conversion and gamma correction are not included */ struct intel_vgpu_primary_plane_format { u8 enabled; /* plane is enabled */ - u8 tiled; /* X-tiled */ + u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */ u8 bpp; /* bits per pixel */ u32 hw_format; /* format field in the PRI_CTL register */ u32 drm_format; /* format in DRM definition */ |