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authorZhao Yan <yan.y.zhao@intel.com>2017-03-09 05:09:44 +0300
committerZhenyu Wang <zhenyuw@linux.intel.com>2017-03-17 11:46:45 +0300
commit4938ca90166d6d3061793789e2eef42cd934fa97 (patch)
tree467da64107cd9022a813038d5018171e43e05765 /drivers/gpu/drm/i915/gvt/mmio.h
parent6aef660370a9c246956ba6d01eebd8063c4214cb (diff)
downloadlinux-4938ca90166d6d3061793789e2eef42cd934fa97.tar.xz
drm/i915/gvt: handle force-nonpriv registers, cmd parser part
this patch adds force non-priv registers check in LRI cmds handler v4: transform is_force_nonpriv_mmio() from macro to inline fuction to eliminate checkpatch warning v3: per zhenyu's comment, fix some style warnings v2: per zhenyu's comment, refine the code to remove cascaded ifs Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/mmio.h')
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
index 3bc620f56f35..a3a027025cd0 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.h
+++ b/drivers/gpu/drm/i915/gvt/mmio.h
@@ -107,4 +107,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes);
int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes);
+
+bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
+ unsigned int offset);
#endif