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| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2022-10-27 01:21:01 +0300 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2022-10-27 22:37:02 +0300 |
| commit | 0fa9349dda030fa847b36f880a5eea25c3202b66 (patch) | |
| tree | d25bb9391bd35c3e61bee0725f4bafcb79b6bdaf /drivers/gpu/drm/i915/intel_device_info.h | |
| parent | 01e7427467857861d1aaa7cd05598dfcb631c5b5 (diff) | |
| download | linux-0fa9349dda030fa847b36f880a5eea25c3202b66.tar.xz | |
drm/i915/perf: complete programming whitelisting for XEHPSDV
We have an additional register to select which slices contribute to
OAG/OAG counter increments.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-16-umesh.nerlige.ramappa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_device_info.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_device_info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index d11546d87fe7..4ee6074955ef 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -164,6 +164,7 @@ enum intel_ppgtt_type { func(has_media_ratio_mode); \ func(has_mslice_steering); \ func(has_oa_bpc_reporting); \ + func(has_oa_slice_contrib_limits); \ func(has_one_eu_per_fuse_bit); \ func(has_pxp); \ func(has_rc6); \ |