diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-12-01 18:25:44 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-01-18 04:46:59 +0300 |
| commit | 12d7d858e63d0769a91aab218828e0526c0ab49d (patch) | |
| tree | 7005c848cd0efe865b710331f8693ab8c553ea13 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 71b59439aa03e8de022c31ccbf9aa9bea4578971 (diff) | |
| download | linux-12d7d858e63d0769a91aab218828e0526c0ab49d.tar.xz | |
drm/i915: Use REG_BIT() & co. for universal plane bits
Polish the skl+ universal plane register defines by
using REG_BIT() & co.
The defines are also currently spread around in some
semi-random fashion. Collect them up into one place.
v2: deal with gvt
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-7-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a83b71af551b..897d66fec5d6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4292,11 +4292,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv, struct skl_ddb_entry *entry, u32 reg) { - entry->start = reg & DDB_ENTRY_MASK; - entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK; - + entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg); + entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg); if (entry->end) - entry->end += 1; + entry->end++; } static void @@ -4320,7 +4319,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, /* No DDB allocated for disabled planes */ if (val & PLANE_CTL_ENABLE) - fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK, + fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL, val & PLANE_CTL_ORDER_RGBX, val & PLANE_CTL_ALPHA_MASK); @@ -5891,7 +5890,8 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, { if (entry->end) intel_de_write_fw(dev_priv, reg, - (entry->end - 1) << 16 | entry->start); + PLANE_BUF_END(entry->end - 1) | + PLANE_BUF_START(entry->start)); else intel_de_write_fw(dev_priv, reg, 0); } |