diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2022-01-21 02:50:16 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-02-02 00:07:45 +0300 |
| commit | 86df4141869350edaa53fb994b3db2c2cca5065d (patch) | |
| tree | ef4ff1d8d4f048fffd01c2c524633ce38104f60b /drivers/gpu/drm/i915/intel_step.c | |
| parent | 29b9702ffe70d83b9970abbccaeb287dfda4409f (diff) | |
| download | linux-86df4141869350edaa53fb994b3db2c2cca5065d.tar.xz | |
drm/i915: Introduce G12 subplatform of DG2
Another fork of the DG2 design has appeared, known as "DG2-G12;" let's
add it as a new subplatform. As with G11, the GT stepping resets back
to A0 (so a DG2-G12 A0 is similar, but not identical, to a DG2-G10 C0)
but the display steppings continue to use the same numbering scheme as
G10 and G11.
Some existing DG2 workarounds are starting to be extended to the DG2-G12
subplatform. So far only workarounds that were "permanent" for both
DG2-G10 and DG2-G11 have been tagged for DG2-G12, but more
stepping-specific workarounds are likely to show up in the future.
Bspec: 44477
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120235016.1209326-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_step.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_step.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 453c04472545..ac1a796b2808 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -122,6 +122,10 @@ static const struct intel_step_info dg2_g11_revid_step_tbl[] = { [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, }; +static const struct intel_step_info dg2_g12_revid_step_tbl[] = { + [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 }, +}; + static const struct intel_step_info adls_rpls_revids[] = { [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 }, [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 }, @@ -140,6 +144,9 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_DG2_G11(i915)) { revids = dg2_g11_revid_step_tbl; size = ARRAY_SIZE(dg2_g11_revid_step_tbl); + } else if (IS_DG2_G12(i915)) { + revids = dg2_g12_revid_step_tbl; + size = ARRAY_SIZE(dg2_g12_revid_step_tbl); } else if (IS_XEHPSDV(i915)) { revids = xehpsdv_revids; size = ARRAY_SIZE(xehpsdv_revids); |