diff options
| author | Marijn Suijten <marijn.suijten@somainline.org> | 2022-12-22 02:19:42 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-12 22:45:17 +0300 |
| commit | 7aa6f1a12ff4439a5d7e8b877d57d78c2a86d3ee (patch) | |
| tree | ef9552d800a090e9acfe52852ee4b8ae8efe4fed /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | |
| parent | 4ba5a4ad568e3b2396dca307894062b7e9442e61 (diff) | |
| download | linux-7aa6f1a12ff4439a5d7e8b877d57d78c2a86d3ee.tar.xz | |
drm/msm/dpu: Implement DSC binding to PP block for CTL V1
All V1 CTL blocks (active CTLs) explicitly bind the pixel output from a
DSC block to a PINGPONG block by setting the PINGPONG index in a DSC
hardware register.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/515698/
Link: https://lore.kernel.org/r/20221221231943.1961117-8-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 3662df698dae..619926da1441 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -29,6 +29,8 @@ #define DSC_RANGE_MAX_QP 0x0B0 #define DSC_RANGE_BPG_OFFSET 0x0EC +#define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0)) + static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) { struct dpu_hw_blk_reg_map *c = &dsc->hw; @@ -150,6 +152,29 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, } } +static void dpu_hw_dsc_bind_pingpong_blk( + struct dpu_hw_dsc *hw_dsc, + bool enable, + const enum dpu_pingpong pp) +{ + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; + int mux_cfg = 0xF; + u32 dsc_ctl_offset; + + dsc_ctl_offset = DSC_CTL(hw_dsc->idx); + + if (enable) + mux_cfg = (pp - PINGPONG_0) & 0x7; + + DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n", + enable ? "Binding" : "Unbinding", + hw_dsc->idx - DSC_0, + enable ? "to" : "from", + pp - PINGPONG_0); + + DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); +} + static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -174,6 +199,8 @@ static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, ops->dsc_disable = dpu_hw_dsc_disable; ops->dsc_config = dpu_hw_dsc_config; ops->dsc_config_thresh = dpu_hw_dsc_config_thresh; + if (cap & BIT(DPU_DSC_OUTPUT_CTRL)) + ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; }; struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, |