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authorKonrad Dybcio <konrad.dybcio@linaro.org>2023-09-26 21:24:36 +0300
committerRob Clark <robdclark@chromium.org>2023-10-09 21:22:05 +0300
commit75cb60d4f5f762b12643b67cbefefcf05ecfd7eb (patch)
tree272ed995f08e1e4ecc9c93206a1cb6e3f64e3ecf /drivers/gpu/drm/msm
parentbeb3542320479cd59a08273be0b19dfea0b36042 (diff)
downloadlinux-75cb60d4f5f762b12643b67cbefefcf05ecfd7eb.tar.xz
drm/msm/a6xx: Fix unknown speedbin case
When opp-supported-hw is present under an OPP node, but no form of opp_set_supported_hw() has been called, that OPP is ignored by the API and marked as unsupported. Before Commit c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table"), an unknown speedbin would result in marking all OPPs as available, but it's better to avoid potentially overclocking the silicon - the GMU will simply refuse to power up the chip. Currently, the Adreno speedbin code does just that (AND returns an invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0 (which is conveniently always bound to fuseval == 0). Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559604/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm')
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 11cb410e0ac7..7a0220d29a23 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2730,7 +2730,7 @@ static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *i
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
speedbin);
- return UINT_MAX;
+ supp_hw = BIT(0); /* Default */
}
ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);