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| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-09-22 14:06:49 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-11-02 11:48:18 +0300 |
| commit | 0a30e150f053e609f7820d81efebde28802035f3 (patch) | |
| tree | 1f108d6ea7fdf9b6019fd092a0799996dd87b8a1 /drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | |
| parent | 4dc2250d7d9e816b986d656cde90f55c096012ed (diff) | |
| download | linux-0a30e150f053e609f7820d81efebde28802035f3.tar.xz | |
drm/omap: omap_display_timings: rename hfp to hfront_porch
In preparation to move the stack to use the generic videmode struct for
display timing information rename the hfp member to hfront_porch.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss/hdmi5_core.c')
| -rw-r--r-- | drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c index dd4c989c44ce..26012224e7e4 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c @@ -296,7 +296,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, /* video core */ video_cfg->data_enable_pol = 1; /* It is always 1*/ - video_cfg->hblank = cfg->timings.hfp + + video_cfg->hblank = cfg->timings.hfront_porch + cfg->timings.hbp + cfg->timings.hsync_len; video_cfg->vblank_osc = 0; video_cfg->vblank = cfg->timings.vsw + @@ -318,7 +318,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, if (cfg->timings.double_pixel) { video_cfg->v_fc_config.timings.hactive *= 2; video_cfg->hblank *= 2; - video_cfg->v_fc_config.timings.hfp *= 2; + video_cfg->v_fc_config.timings.hfront_porch *= 2; video_cfg->v_fc_config.timings.hsync_len *= 2; video_cfg->v_fc_config.timings.hbp *= 2; } @@ -367,9 +367,9 @@ static void hdmi_core_video_config(struct hdmi_core_data *core, /* set horizontal sync offset */ REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, - cfg->v_fc_config.timings.hfp >> 8, 4, 0); + cfg->v_fc_config.timings.hfront_porch >> 8, 4, 0); REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, - cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); + cfg->v_fc_config.timings.hfront_porch & 0xFF, 7, 0); /* set vertical sync offset */ REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, |